;Register definition for MCF5235 ;=============================== ; ; name: user defined name of the register ; type: the type of the register ; DREG data register ; AREG address register ; CREG control register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; ; Additional Control Register ; other_a7 CREG 0x800 32 macsr CREG 0x804 8 mask CREG 0x805 16 acc0 CREG 0x806 16 accext01 CREG 0x807 16 accext23 CREG 0x808 16 acc1 CREG 0x809 16 acc2 CREG 0x80a 16 acc3 CREG 0x80b 16 flashbar CREG 0xc04 32 rambar CREG 0xc05 32 ; ; ; ; DMM1 must be set to the internal memory base address ; ; SDRAMC Registers dcr DMM1 0x040 16 dacr0 DMM1 0x048 32 dmr0 DMM1 0x04C 32 dacr1 DMM1 0x050 32 dmr1 DMM1 0x054 32 ; ; Chip Select Registers csar0 DMM1 0x080 16 csmr0 DMM1 0x084 32 cscr0 DMM1 0x08A 16 csar1 DMM1 0x08C 16 csmr1 DMM1 0x090 32 cscr1 DMM1 0x096 16 csar2 DMM1 0x098 16 csmr2 DMM1 0x09C 32 cscr2 DMM1 0x0A2 16 csar3 DMM1 0x0A4 16 csmr3 DMM1 0x0A8 32 cscr3 DMM1 0x0AE 16 csar4 DMM1 0x0B0 16 csmr4 DMM1 0x0B4 32 cscr4 DMM1 0x0BA 16 csar5 DMM1 0x0BC 16 csmr5 DMM1 0x0C0 32 cscr5 DMM1 0x0C6 16 csar6 DMM1 0x0C8 16 csmr6 DMM1 0x0CC 32 cscr6 DMM1 0x0D2 16 ; ; Watchdog Timer Registers wcr DMM1 0x140000 16 wmr DMM1 0x140002 16 wcntr DMM1 0x140004 16 wsr DMM1 0x140006 16