;Register definition for MCF5223 ;=============================== ; ; name: user defined name of the register ; type: the type of the register ; DREG data register ; AREG address register ; CREG control register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; ; Additional Control Register ; other_a7 CREG 0x800 32 macsr CREG 0x804 8 mask CREG 0x805 16 acc0 CREG 0x806 16 accext01 CREG 0x807 16 accext23 CREG 0x808 16 acc1 CREG 0x809 16 acc2 CREG 0x80a 16 acc3 CREG 0x80b 16 flashbar CREG 0xc04 32 rambar CREG 0xc05 32 ; ; ; ; DMM1 must be set to the internal memory base address ; ; SCM Registers ipsbar DMM1 0x000 32 ppmrl DMM1 0x008 32 ppmrh DMM1 0x00C 32 crsr DMM1 0x010 8 cwcr DMM1 0x011 8 lpicr DMM1 0x012 8 cwsr DMM1 0x013 8 dmareqc DMM1 0x014 32 ppmrl DMM1 0x018 32 mpark DMM1 0x01C 32 mpr DMM1 0x020 32 ppmrs DMM1 0x021 8 ppmrc DMM1 0x022 8 pacr0 DMM1 0x024 8 pacr1 DMM1 0x025 8 pacr2 DMM1 0x026 8 pacr3 DMM1 0x027 8 pacr4 DMM1 0x028 8 pacr5 DMM1 0x02A 8 pacr6 DMM1 0x02B 8 pacr7 DMM1 0x02C 8 pacr8 DMM1 0x02E 8 gpacr0 DMM1 0x030 8 gpacr1 DMM1 0x031 8 ; ; DMA Registers sar0 DMM1 0x100 32 dar0 DMM1 0x104 32 dcr0 DMM1 0x108 8 bcr01 DMM1 0x108 32 dsr0 DMM1 0x10C 8 sar1 DMM1 0x140 32 dar1 DMM1 0x144 32 dcr1 DMM1 0x148 8 bcr1 DMM1 0x148 32 dsr1 DMM1 0x14C 8 sar2 DMM1 0x180 32 dar2 DMM1 0x184 32 dcr2 DMM1 0x188 8 bcr2 DMM1 0x188 32 dsr2 DMM1 0x18C 8 sar3 DMM1 0x1C0 32 dar3 DMM1 0x1C4 32 dcr3 DMM1 0x1C8 8 bcr3 DMM1 0x1C8 32 dsr3 DMM1 0x1CC 8 ; ; I2C Registers i2adr DMM1 0x300 8 i2fdr DMM1 0x304 8 i2cr DMM1 0x308 8 i2sr DMM1 0x30C 8 i2dr DMM1 0x310 8 ; ; QSPI Registers qmr DMM1 0x340 16 qdlyr DMM1 0x344 16 qwr DMM1 0x348 16 qir DMM1 0x34C 16 qar DMM1 0x350 16 qdr DMM1 0x354 16 ; ; DMA Timer Registers dtmr0 DMM1 0x400 16 dtxmr0 DMM1 0x402 8 dter0 DMM1 0x403 8 dtrr0 DMM1 0x404 32 dtcr0 DMM1 0x408 32 dtcn0 DMM1 0x40C 32 dtmr1 DMM1 0x440 16 dtxmr1 DMM1 0x442 8 dter1 DMM1 0x443 8 dtrr1 DMM1 0x444 32 dtcr1 DMM1 0x448 32 dtcn1 DMM1 0x44C 32 dtmr2 DMM1 0x480 16 dtxmr2 DMM1 0x482 8 dter2 DMM1 0x483 8 dtrr2 DMM1 0x484 32 dtcr2 DMM1 0x488 32 dtcn2 DMM1 0x48C 32 dtmr3 DMM1 0x4C0 16 dtxmr3 DMM1 0x4C2 8 dter3 DMM1 0x4C3 8 dtrr3 DMM1 0x4C4 32 dtcr3 DMM1 0x4C8 32 dtcn3 DMM1 0x4CC 32 ; ; Interrupt Controller 0 iprh0 DMM1 0xC00 32 iprl0 DMM1 0xC04 32 imrh0 DMM1 0xC08 32 imrl0 DMM1 0xC0C 32 intfrch0 DMM1 0xC10 32 intfrcl0 DMM1 0xC14 32 ilrr0 DMM1 0xC18 8 iacklpr0 DMM1 0XC19 8 ; icr001 DMM1 0xC41 8 icr002 DMM1 0xC42 8 icr003 DMM1 0xC43 8 icr004 DMM1 0xC44 8 icr005 DMM1 0xC45 8 icr006 DMM1 0xC46 8 icr007 DMM1 0xC47 8 icr008 DMM1 0xC48 8 icr009 DMM1 0xC49 8 icr010 DMM1 0xC4A 8 icr011 DMM1 0xC4B 8 icr012 DMM1 0xC4C 8 icr013 DMM1 0xC4D 8 icr014 DMM1 0xC4E 8 icr015 DMM1 0xC4F 8 icr017 DMM1 0xC51 8 icr018 DMM1 0xC52 8 icr019 DMM1 0xC53 8 icr020 DMM1 0xC54 8 icr021 DMM1 0xC55 8 icr022 DMM1 0xC56 8 icr023 DMM1 0xC57 8 icr024 DMM1 0xC58 8 icr025 DMM1 0xC59 8 icr026 DMM1 0xC5A 8 icr027 DMM1 0xC5B 8 icr028 DMM1 0xC5C 8 icr029 DMM1 0xC5D 8 icr030 DMM1 0xC5E 8 icr031 DMM1 0xC5F 8 icr032 DMM1 0xC60 8 icr033 DMM1 0xC61 8 icr034 DMM1 0xC62 8 icr035 DMM1 0xC63 8 icr036 DMM1 0xC64 8 icr037 DMM1 0xC65 8 icr038 DMM1 0xC66 8 icr039 DMM1 0xC67 8 icr040 DMM1 0xC68 8 icr041 DMM1 0xC69 8 icr042 DMM1 0xC6A 8 icr043 DMM1 0xC6B 8 icr044 DMM1 0xC6C 8 icr045 DMM1 0xC6D 8 icr046 DMM1 0xC6E 8 icr047 DMM1 0xC6F 8 icr048 DMM1 0xC70 8 icr049 DMM1 0xC71 8 icr050 DMM1 0xC72 8 icr051 DMM1 0xC73 8 icr052 DMM1 0xC74 8 icr053 DMM1 0xC75 8 icr054 DMM1 0xC76 8 icr055 DMM1 0xC77 8 icr056 DMM1 0xC78 8 icr057 DMM1 0xC79 8 icr058 DMM1 0xC7A 8 icr059 DMM1 0xC7B 8 icr060 DMM1 0xC7C 8 icr061 DMM1 0xC7D 8 icr062 DMM1 0xC7E 8 ; ; Reset Control, Chip Configuration, and Power Management Registers rcr DMM1 0x110000 8 rsr DMM1 0x110001 8 ccr DMM1 0x110004 16 lpcr DMM1 0x110007 8 rcon DMM1 0x110008 16 cir DMM1 0x11000A 16 rtcdf DMM1 0x11000C 32 ; ; Clock Module Registers syncr DMM1 0x120000 16 synsr DMM1 0x120002 8 lpdr DMM1 0x120007 8 cchr DMM1 0x120008 8 rtcdr DMM1 0x12000C 32 ; ; Edge Port Registers eppar0 DMM1 0x130000 16 epddr0 DMM1 0x130002 8 epier0 DMM1 0x130003 8 epdr0 DMM1 0x130004 8 eppdr0 DMM1 0x130005 8 epfr0 DMM1 0x130006 8 ; eppar1 DMM1 0x140000 16 epddr1 DMM1 0x140002 8 epier1 DMM1 0x140003 8 epdr1 DMM1 0x140004 8 eppdr1 DMM1 0x140005 8 epfr1 DMM1 0x140006 8 ; ; Programmable Interrupt Timer Registers pcsr0 DMM1 0x150000 16 pmr0 DMM1 0x150002 16 pcntr0 DMM1 0x150004 16 pcsr1 DMM1 0x160000 16 pmr1 DMM1 0x160002 16 pcntr1 DMM1 0x160004 16 ; ; General Purpose Timer Registers gptios DMM1 0x1A0000 8 gptcforc DMM1 0x1A0001 8 gptoc3m DMM1 0x1A0002 8 gptoc3d DMM1 0x1A0003 8 gptcnt DMM1 0x1A0004 16 gptscr1 DMM1 0x1A0006 8 gpttov DMM1 0x1A0008 8 gptctl1 DMM1 0x1A0009 8 gptctl2 DMM1 0x1A000B 8 gptie DMM1 0x1A000C 8 gptscr2 DMM1 0x1A000D 8 gptflg1 DMM1 0x1A000E 8 gptflg2 DMM1 0x1A000F 8 gptc0 DMM1 0x1A0010 16 gptc1 DMM1 0x1A0012 16 gptc2 DMM1 0x1A0014 16 gptc3 DMM1 0x1A0016 16 gptpactl DMM1 0x1A0018 8 gptpaflg DMM1 0x1A0019 8 gptpacnt DMM1 0x1A001A 8 gptport DMM1 0x1A001D 8 gptddr DMM1 0x1A001E 8 ; ; Flash Registers cfmmcr DMM1 0x1D0000 16 cfmclkd DMM1 0x1D0002 8 cfmsec DMM1 0x1D0008 32 cfmprot DMM1 0x1D0010 32 cfmsacc DMM1 0x1D0014 32 cfmdacc DMM1 0x1D0018 32 cfmustat DMM1 0x1D0020 8 cfmcmd DMM1 0x1D0024 8 cfmclksel DMM1 0x1D004A 16 ;