;Register definition for MCF5206 ;=============================== ; ; name: user defined name of the register ; type: the type of the register ; DREG data register ; AREG address register ; CREG control register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; ; ; DMM1 must be set to the internal memory base address ; ; System Integration Module simr DMM1 0x003 8 icr1 DMM1 0x014 8 icr2 DMM1 0x015 8 icr3 DMM1 0x016 8 icr4 DMM1 0x017 8 icr5 DMM1 0x018 8 icr6 DMM1 0x019 8 icr7 DMM1 0x01a 8 icr8 DMM1 0x01b 8 icr9 DMM1 0x01c 8 icr10 DMM1 0x01d 8 icr11 DMM1 0x01e 8 icr12 DMM1 0x01f 8 icr13 DMM1 0x020 8 imr DMM1 0x036 16 ipr DMM1 0x03a 16 rsr DMM1 0x040 8 sypcr DMM1 0x041 8 swivr DMM1 0x042 8 swsr DMM1 0x044 8 ; ; DRAM Controller Module dcrr DMM1 0x046 16 dctr DMM1 0x04a 16 dcar0 DMM1 0x04c 16 dcmr0 DMM1 0x050 32 dccr0 DMM1 0x057 8 dcar1 DMM1 0x058 16 dcmr1 DMM1 0x05c 32 dccr1 DMM1 0x063 8 ; ; Chip Select Module csar0 DMM1 0x064 16 csmr0 DMM1 0x068 32 cscr0 DMM1 0x06e 16 csar1 DMM1 0x070 16 csmr1 DMM1 0x074 32 cscr1 DMM1 0x07a 16 csar2 DMM1 0x07c 16 csmr2 DMM1 0x080 32 cscr2 DMM1 0x086 16 csar3 DMM1 0x088 16 csmr3 DMM1 0x08c 32 cscr3 DMM1 0x092 16 csar4 DMM1 0x094 16 csmr4 DMM1 0x098 32 cscr4 DMM1 0x09e 16 csar5 DMM1 0x0a0 16 csmr5 DMM1 0x0a4 32 cscr5 DMM1 0x0aa 16 csar6 DMM1 0x0ac 16 csmr6 DMM1 0x0b0 32 cscr6 DMM1 0x0b6 16 csar7 DMM1 0x0b8 16 csmr7 DMM1 0x0bc 32 cscr7 DMM1 0x0c2 16 dmcr DMM1 0x0c6 16 par DMM1 0x0ca 16 ; ; ; Timer Module tmr1 DMM1 0x100 16 trr1 DMM1 0x104 16 tcr1 DMM1 0x108 16 tcn1 DMM1 0x10c 16 ter1 DMM1 0x111 8 tmr2 DMM1 0x120 16 trr2 DMM1 0x124 16 tcr2 DMM1 0x128 16 tcn2 DMM1 0x12c 16 ter2 DMM1 0x131 8