; Configuration file for a phyCORE-MCF5485 board
; ----------------------------------------------
;
[INIT]
;
;	=== Set Memory Map ===
WCREG   0xC0F       0x10000001	;MBAR   : map internal REGS to 0x10000000
WCREG   0x008       0x11000001	;MMUBAR : map MMU registers to 0x11000000
WCREG   0xC04       0x20000021	;RAMBAR0: map internal SRAM to 0x20000000
WCREG   0xC05       0x20001021	;RAMBAR1: map internal SRAM to 0x20001000
WCREG   0x802       0x00000000	;VBR    : map vector table  to 0x00000000
;
;	=== Flash Chipselect ===
WM32	0x10000500  0xFE000000	;CSAR0: Flash at 0xFE000000
WM32	0x10000508  0x00001900	;CSCR0: 32bit
WM32	0x10000504  0x01FF0001	;CSMR0: Flash 32MB, R/W, valid
;
;	=== DDR SDRAM 128MB ===
WM32	0x10000004  0x000002AA	;SDRAMDS : SSTL 2 Class 1
WM32	0x10000020  0x0000001A	;CS0CFG : 128MByte
WM32	0x10000024  0x00000000	;CS1CFG
WM32	0x10000028  0x00000000	;CS2CFG
WM32	0x1000002C  0x00000000	;CS3CFG
WM32	0x10000108  0x53722930	;SDCFG1
WM32	0x1000010C  0x24330000	;SDCFG2
;
WM32	0x10000104  0xE10F0002	;SDCR + IPALL
WM32	0x10000100  0x40010000	;SDMR (write to LEMR)
WM32	0x10000100  0x05890000	;SDRM (write to LMR)
WM32	0x10000104  0xE10F0002	;SDCR + IPALL
WM32	0x10000104  0xE10F0004	;SDCR + IREF (first refresh)
WM32	0x10000104  0xE10F0004	;SDCR + IREF (second refresh)
WM32	0x10000100  0x01890000	;SDMR (write to LMR)
WM32	0x10000104  0x710F0F00	;SDCR (lock SDMR and enable refresh)
DELAY   1000
;
WAREG   7           0x000ffff0  ;set initial SP
WAREG   6           0x000ffff0  ;set initial FP
;
;	=== MMU : Map direct access via ACR's ===
WCREG   0x004       0x0007C000	;ACR0 : Map 128 MB DDR SDRAM, WT
WCREG   0x006       0x0007C000	;ACR2 : Map 128 MB DDR SDRAM, WT
WCREG   0x005       0xFE01C040	;ACR1 : Map  32 MB Flash, WT
WCREG   0x007       0xFE01C040	;ACR3 : Map  32 MB Flash, WT
;
;	=== MMU : Map internal registers ===
WTLB	0x10000001  0x10000298	;0x10000000 -> 0x10000000, 8k, NP, RW-
WTLB	0x10002001  0x10020298	;0x10002000 -> 0x10002000, 8k, NP, RW-
WTLB	0x10004001  0x10040298	;0x10004000 -> 0x10004000, 8k, NP, RW-
WTLB	0x10006001  0x10060298	;0x10006000 -> 0x10006000, 8k, NP, RW-
WTLB	0x10008001  0x10080298	;0x10008000 -> 0x10008000, 8k, NP, RW-
WTLB	0x1000A001  0x100A0298	;0x1000A000 -> 0x1000A000, 8k, NP, RW-
WTLB	0x1000C001  0x100C0298	;0x1000C000 -> 0x1000C000, 8k, NP, RW-
WTLB	0x1000E001  0x100E0298	;0x1000E000 -> 0x1000E000, 8k, NP, RW-
;
;	=== MMU : Map DDR SDRAM to 0xC0000000 ===
WTLB	0xC0000003  0x0000005C	;0xC0000000 -> 0x00000000, 1MB, CB, RWX
WTLB	0xC0100003  0x0010005C	;0xC0100000 -> 0x00100000, 1MB, CB, RWX
WTLB	0xC0200003  0x0020005C	;0xC0200000 -> 0x00200000, 1MB, CB, RWX
WTLB	0xC0300003  0x0030005C	;0xC0300000 -> 0x00300000, 1MB, CB, RWX
;
WM32	0x11000000  0x00000001	;MMUCR: enable MMU
;


[TARGET]
CPUTYPE     MCF5480
CPUCLOCK    100000000   ;the PSTCLK clock rate after processing the init list
WAKEUP      10          ;give reset time to complete
;BREAKMODE   HARD        ;SOFT or HARD
BREAKMODE   SOFT        ;SOFT or HARD
;VECTOR      CATCH       ;catch unhandled exceptions
MMU         XLAT        ;enable address translation

[HOST]
IP          151.120.25.119
FILE        E:\cygwin\home\demo\mcf\fibo.x
FORMAT      ELF
LOAD        MANUAL      ;load code MANUAL or AUTO after reset
DUMP        E:\temp\dump.bin
PROMPT      phy5485>

[FLASH]
WORKSPACE   0x10010000  ;workspace in internal SRAM
CHIPTYPE    STRATAX16   ;Flash type is 28F128K3C
CHIPSIZE    0x01000000  ;The size of one flash chip in bytes
BUSWIDTH    32          ;The width of the flash memory bus in bits (8 | 16 | 32)
FILE        E:\temp\dump512k.bin
FORMAT      BIN 0xFE800000
ERASE       0xFE800000  UNLOCK  ;unlock/erase a sector
ERASE       0xFE840000  UNLOCK  ;unlock/erase a sector
ERASE       0xFE880000  UNLOCK  ;unlock/erase a sector
ERASE       0xFE8C0000  UNLOCK  ;unlock/erase a sector


[REGS]
CMM1	0xC0F 0xfffc0000        ;MBAR
CMM2	0x008 0xffff0000        ;MMUBAR
FILE    $reg5485.def