; Configuration file for a MCF5485EVB board
; -----------------------------------------
;
[INIT]
;
;	=== Set Memory Map ===
WCREG   0xC0F       0x10000001	;MBAR   : map internal REGS to 0x10000000
WCREG   0x008       0x11000001	;MMUBAR : map MMU registers to 0x11000000
WCREG   0xC04       0x20000035	;RAMBAR0: map internal SRAM to 0x20000000 (data only)
WCREG   0xC05       0x20001035	;RAMBAR1: map internal SRAM to 0x20001000 (data only)
;
;	=== Flash Chipselect ===
WM16	0x10000500  0x7E00	;CSAR0: Flash at 0x7E000000
WM32	0x10000508  0x003ffd00	;CSCR0: Flash 63 waits, 32bit,
WM32	0x10000504  0x01FF0001	;CSMR0: Flash 32MB, R/W, valid
;
;	=== Fast SRAM Chipselect ===
WM16	0x1000050C  0x0000	;CSAR1: FSRAM 0x00000000
WM32	0x10000514  0x003ffd00	;CSCR1: FSRAM 63 waits, 32bit,
WM32	0x10000510  0x00070001	;CSMR1: FSRAM 512K, R/W, valid
;
WAREG   7           0x10017ff0  ;set initial SP
WAREG   6           0x10017ff0  ;set initial FP
;
;	=== MMU : Map internal registers ===
WTLB	0x10000001  0x10000298	;0x10000000 -> 0x10000000, 8k, NP, RW-
WTLB	0x10002001  0x10020298	;0x10002000 -> 0x10002000, 8k, NP, RW-
WTLB	0x10004001  0x10040298	;0x10004000 -> 0x10004000, 8k, NP, RW-
WTLB	0x10006001  0x10060298	;0x10006000 -> 0x10006000, 8k, NP, RW-
WTLB	0x10008001  0x10080298	;0x10008000 -> 0x10008000, 8k, NP, RW-
WTLB	0x1000A001  0x100A0298	;0x1000A000 -> 0x1000A000, 8k, NP, RW-
WTLB	0x1000C001  0x100C0298	;0x1000C000 -> 0x1000C000, 8k, NP, RW-
WTLB	0x1000E001  0x100E0298	;0x1000E000 -> 0x1000E000, 8k, NP, RW-
;	=== MMU : Map 32k System RAM to 0x00000000 ===
WTLB	0x00000001  0x1001025C	;0x00000000 -> 0x10010000, 8k, CB, RWX
WTLB	0x00002001  0x1001225C	;0x00002000 -> 0x10012000, 8k, CB, RWX
WTLB	0x00004001  0x1001425C	;0x00004000 -> 0x10014000, 8k, CB, RWX
WTLB	0x00006001  0x1001625C	;0x00008000 -> 0x10016000, 8k, CB, RWX
;
WM32	0x11000000  0x00000001	;MMUCR: enable MMU
;
WAREG   7           0x00007ff0  ;set initial SP
WAREG   6           0x00007ff0  ;set initial FP
;


[TARGET]
CPUTYPE     MCF5480
CPUCLOCK    120000000   ;the PSTCLK clock rate after processing the init list
WAKEUP      10          ;M5485EVB board requires a reset wakeup delay for robust reset
                        ;This may not be required for other boards using this processor
;BREAKMODE   HARD        ;SOFT or HARD
BREAKMODE   SOFT        ;SOFT or HARD


[HOST]
IP          151.120.25.119
FILE        E:\cygwin\home\demo\mcf\fibo.x
FORMAT      ELF
LOAD        MANUAL      ;load code MANUAL or AUTO after reset
DUMP        E:\temp\dump.bin

[FLASH]
WORKSPACE   0x10010000  ;workspace in internal SRAM
CHIPTYPE    MIRRORX16   ;Flash type is AM29LV128MH
CHIPSIZE    0x01000000  ;The size of one flash chip in bytes
BUSWIDTH    32          ;The width of the flash memory bus in bits (8 | 16 | 32)
FILE        E:\cygwin\home\bdidemo\coldfire\mcf5485.cfg
FORMAT      BIN 0x7E000000


[REGS]
CMM1	0xC0F 0xfffc0000        ;MBAR
CMM2	0x008 0xffff0000        ;MMUBAR
FILE    $reg5485.def