; Configuration file for the M5329EVB (Zoom) ; ------------------------------------------ ; ; the initialistion list used to setup the target system [INIT] ; WCREG 0x801 0x40000000 ;VBR: Set VBR to the beginning of SDRAM WCREG 0xC05 0x80000221 ;RAMBAR: Internal SRAM at 0x80000000 WM16 0xFC098000 0x0000 ;WCR: Disable Watchdog ; ; Init flash chip select WM32 0xFC008000 0x00000000 ;CSAR0: map to 0x00000000 WM32 0xFC008008 0x00001FA0 ;CSCR0: 16-bit port, 7 wait states WM32 0xFC008004 0x001F0001 ;CSMR0: size is 2 MB r/w ; ;SDRAM Initialization WM32 0xFC0B8110 0x4000001A ;SDCS0: 128MB at 0x40000000 WM32 0xFC0B8008 0x43711630 ;SDCFG1 WM32 0xFC0B800C 0x56670000 ;SDCFG2 WM32 0xFC0B8004 0xE1482002 ;SDCR: Issue PALL WM32 0xFC0B8000 0x40010000 ;SDMR: Issue LEMR WM32 0xFC0B8000 0x058D0000 ;SDMR: Write mode register DELAY 100 WM32 0xFC0B8004 0xE1482002 ;SDCR: Issue PALL WM32 0xFC0B8004 0xE1482004 ;SDCR: Perform two refresh cycles WM32 0xFC0B8004 0xE1482004 ;SDCR WM32 0xFC0B8000 0x018D0000 ;SDMR WM32 0xFC0B8004 0x71482C00 ;SDCR DELAY 100 ; ; === Define the valid memory map === MMAP 0x00000000 0x001FFFFF ; 2MB Flash MMAP 0x40000000 0x47FFFFFF ;128MB SDRAM MMAP 0x80000000 0x80007FFF ; 32KB Internal SRAM MMAP 0xFC000000 0xFFFFFFFF ;Peripheral Registers ; [TARGET] CPUTYPE MCF5329 CPUCLOCK 180000000 ;the CPU clock rate after processing the init list BREAKMODE HARD NOUHE ;SOFT or HARD, HALT is supervisor only instruction ;WAKEUP 1000 [HOST] IP 151.120.25.119 FILE E:\cygwin\home\demo\mcf\fibo.x FORMAT ELF LOAD MANUAL ;load code MANUAL or AUTO after reset PROMPT 5329> [FLASH] WORKSPACE 0x80000000 ;workspace in internal RAM for fast programming algorithm CHIPTYPE I28BX16 ;Flash type is I28F160C3 CHIPSIZE 0x200000 ;Flash size is 2MB BUSWIDTH 16 ;Flash is used in 16-bit mode ;FILE E:\Cygwin\home\bdidemo\ColdFire\m5329evb.bin ;FORMAT BIN 0x00000000 FILE E:\temp\dump256k.bin FORMAT BIN 0x00140000 ERASE 0x00140000 UNLOCK ERASE 0x00150000 UNLOCK ERASE 0x00160000 UNLOCK ERASE 0x00170000 UNLOCK [REGS] FILE $reg5329.def