; --------------------------------------
; bdiGDB configuration for LM3S with SWO
; --------------------------------------
;
; Supported SWO baudrates above 115200:
;
; BDI2000: 122kb, 130kb, 139kb, 149kb, 160kb, 174kb, 189kb,
;          208kb, 232kb, 260kb, 298kb, 347kb, 417kb, 520kb
;
; BDI3000: 125kb, 133kb, 143kb, 154kb, 167kb, 182kb, 200kb,
;          222kb, 250kb, 285kb, 333kb, 400kb, 500kb
;

[INIT]
WGPR    13      0x2000fffc      ;set SP to top of internal SRAM
;
; setup PLL
WM32    0x400FE060  0x078e3ad1  ;RCC : bypass, internal
WM32    0x400FE070  0x07802810  ;RCC2: bypass, internal
WM32    0x400FE060  0x078e3ad0  ;RCC : enable main oscillator
DELAY   100                     ;let main oscillator startup
WM32    0x400FE060  0x078e0b80  ;RCC : XTAL is 8 MHz, power-up PLL, select main
WM32    0x400FE070  0x07800800  ;RCC2: power-up PLL, select main
WM32    0x400FE060  0x01ce0b80  ;RCC : set SYSDIV for 50MHz
WM32    0x400FE070  0x01800800  ;RCC2: set SYSDIV for 50MHz
DELAY   100                     ;let PLL lock
WM32    0x400FE060  0x01ce0380  ;RCC : clear bypass
WM32    0x400FE070  0x01800000  ;RCC2: clear bypass
WM32    0x400FE060  0x01d40380  ;RCC : set PWMDIV
;
WM32    0x400FE140  49          ;USECRL: Flash USec Reload for 50 MHz
;
; prepare SWO ASCII output via Stimulus0
;
WM32    0xE00400F0  0x00000002  ;TPIU_PROTOCOL  : async mode NRZ
WM32    0xE0040010  99          ;TPIU_PRESCALER : select 500000 baud
WM32    0xE0040304  0x00000100  ;TPIU_FF_CONTROL: formatter bypass
;WM32    0xE0040304  0x00000102  ;TPIU_FF_CONTROL: enable formatter
WM32    0xE0000FB0  0xC5ACCE55  ;ITM_LOCK_ACCESS: enable access
WM32    0xE0000E80  0x00000001  ;ITM_TRACE_CTRL : enable trace
WM32    0xE0000E00  0x00000001  ;ITM_TRACE_ENA  : enable stimulus0
;


[TARGET]
CPUTYPE	    CORTEX-M3
CLOCK       4                   ;BDI3000: JTAG clock 8MHz
POWERUP     1000                ;start delay after power-up detected in ms
RESET	    SOFT                ;assert reset via Reset Control Register
WAKEUP	    100                 ;wait after reset released
STARTUP     HALT                ;halt immediatelly at the reset vector
;STARTUP     RUN                 ;let boot ROM setup the system
ENDIAN      LITTLE              ;memory model (LITTLE | BIG)
BREAKMODE   SOFT                ;SOFT or HARD
MEMACCESS   AHB   1             ;memory access via AHB  (8 TCK's access delay)
VECTOR      CATCH 0x03F0        ;catch all vectors
;
SWO         8023  500000        ;map ASCII SWO to odd  TCP port 8023
;SWO         8020  500000        ;map RAW   SWO to even TCP port 8020
;


[HOST]
IP          151.120.25.112
PROMPT	    SWO-LM3S>
FILE        E:/temp/dump16k.bin
FORMAT      BIN 0x20000000


[FLASH]


[REGS]
FILE        $regLM3S.def