; =======================================
; bdiGDB configuration for IAR LPC1768-SK
; =======================================
;
; Info about the JTAG clock frequency:
; ------------------------------------
; BDI2000:
;   0=Adaptive,
;   1=16MHz, 2=8MHz, 3=4MHz,
;   4= 1MHz, 5=500kHz, 6=200kHz, 7=100kHz, 8=50kHz,
;   9=20kHz, 10=10kHz, 11=5kHz, 12=2kHz, 13=1kHz
; BDI3000:
;   0=Adaptive,
;   1=32MHz, 2=16MHz, 3=11MHz, 4=8MHz, 5=5MHz, 6=4MHz,
;   7=1MHz, 8=500kHz, 9=200kHz, 10=100kHz, 11=50kHz,
;   12=20kHz, 13=10kHz, 14=5kHz, 15=2kHz, 16=1kHz,
;


[INIT]
WGPR    13          0x10007ffc  ;set SP to top of internal SRAM
WM32    0x400FC040  0x00000001  ;MEMMAP: User flash mode
;
; disable PLL0 and select 12MHz oscillator
WM32    0x400FC080  0x00000000  ;PLL0CON: disconnect and disable PLL0
WM32    0x400FC08C  0xaa
WM32    0x400FC08C  0x55
WM32    0x400FC1A0  0x20        ;SCS: enable main oscillator
DELAY   100                     ;give main oscillator time to startup
WM32    0x400FC10C  0x01        ;CLKSRCSEL: select main oscillator
;
; configure and connect PLL0 for CCLK = 96MHz
WM32    0x400FC084  0x00010017  ;PLL0CFG: N=0/M=24 -> Fcco=288MHz
WM32    0x400FC08C  0xaa
WM32    0x400FC08C  0x55
WM32    0x400FC080  0x00000001  ;PLL0CON: enable PLL0
WM32    0x400FC08C  0xaa
WM32    0x400FC08C  0x55
DELAY   100                     ;give PLL0 time to lock
WM32    0x400FC104  0x00000002  ;CCLKCFG: Fcclk = Fcco / 3 = 96MHz
WM32    0x400FC080  0x00000003  ;PLL0CON: connect PLL0
WM32    0x400FC08C  0xaa
WM32    0x400FC08C  0x55
;
; Flash Accelerator Configuration
WM32    0x400FC000  0x00004000  ;FLASHCFG: Flash accesses use 5 CPU clocks
;

[TARGET]
CPUTYPE	    CORTEX-M3
CLOCK       2 7                 ;BDI3000: start with 1 MHz then use 16MHz
;CLOCK       1 4                 ;BDI2000: start with 1 MHz then use 16MHz
POWERUP     1000                ;start delay after power-up detected in ms
RESET	    HARD 100            ;assert reset for 100 ms
;RESET	    SOFT                ;assert reset via Reset Control Register
WAKEUP	    100                 ;wait after reset released
STARTUP     HALT                ;halt immediatelly at the reset vector
;STARTUP     RUN                 ;let boot ROM setup the system
ENDIAN      LITTLE              ;memory model (LITTLE | BIG)
BREAKMODE   SOFT                ;SOFT or HARD
MEMACCESS   AHB   2             ;memory access via AHB  (16 TCK's access delay)
;
;


[HOST]
IP          151.120.25.112
PROMPT	    LPC1768>
FILE        E:/temp/dump16k.bin
FORMAT      BIN 0x10000000
DEBUGPORT   2001 RECONNECT


[FLASH]
CHIPTYPE    LPC1000 96000       ;LPC1000 flash, CCLK = 96.000 MHz
CHIPSIZE    0x80000             ;512kB flash
WORKSPACE   0x10000000          ;internal SRAM for buffer, code and stack
FILE        E:\temp\dump256k.bin
FORMAT      BIN 0x00030000
ERASE       0x0FF00000 BLANK    ;erase sector 20...27 with blank check


[REGS]
FILE    $regLPC1768.def