; ====================================
; bdiGDB configuration for Kinetis L25
; ====================================
;
;

[INIT]
WGPR    13          0x20002ff8  ;set SP to top of internal SRAM
;
; for flash programming disable caches
;WM32    0xF000300C  0x00003c00  ;MCM_PLACR: clear and disable flash cache
;


[TARGET]
CPUTYPE	    CORTEX-M0
CLOCK       8000000             ;JTAG clock 8MHz
POWERUP     3000                ;start delay after power-up detected in ms
RESET	    HARD 100            ;assert reset for 100 ms
WAKEUP	    100                 ;wait after reset released
STARTUP     HALT                ;halt immediatelly at the reset vector
ENDIAN      LITTLE              ;memory model (LITTLE | BIG)
BREAKMODE   SOFT                ;SOFT or HARD
MEMACCESS   AHB   1             ;memory access via AHB  (8 TCK's access delay)
;


[HOST]
PROMPT	    L25>
FILE        E:/temp/dump16k.bin
FORMAT      BIN 0x20000000


[FLASH]
CHIPTYPE    FTFA
WORKSPACE   0x20000000
FILE        E:/temp/dump16k.bin
FORMAT      BIN 0x00010000
ERASE       0x00010000 0x400 16  ;erase 16 x 1kB sectors
;


[REGS]
FILE    $regL25.def