; ------------------------------------------
; Minimal bdiGDB configuration for ZC702 EVM
; ------------------------------------------
;
; Info about the JTAG clock frequency:
; ------------------------------------
; BDI2000:
;   0=Adaptive, 1=16MHz, 2=8MHz, 3=4MHz
;   4=1MHz, 5=500kHz, 6=200kHz, 7=100kHz
;   8=50kHz, 9=20kHz, 10=10kHz
; BDI3000:
;   0=Adaptive, 1=32MHz, 2=16MHz, 3=11MHz,
;   4=8MHz, 5=5MHz, 6=4MHz, 7=1MHz, 8=500kHz
;   9=200kHz, 10=100kHz, 11=50kHz, 12=20kHz,
;   13=10kHz, 14=5kHz, 15=2kHz, 16=1kHz,
;

[INIT]


[TARGET]
POWERUP         2000                    ;start delay after power-up detected in ms
;CLOCK           2                       ;BDI2000: JTAG clock 8MHz
CLOCK           3                       ;BDI3000: JTAG clock 11MHz
TRST            OPENDRAIN               ;TRST driver type (OPENDRAIN | PUSHPULL)
RESET	        NONE                    ;handled via SCANINIT sequence
WAKEUP	        200                     ;wait after reset released

; TRST is actually not connected, but we still toggle it
SCANINIT        r1:w100:t1:w100:t0:     ;assert reset and toggle TRST
SCANINIT        w1000:ch10:w1000:       ;clock TCK with TMS high and wait
SCANINIT        r0:w10000               ;release reset

; CoreID#0 parameters (active core after reset)
#0 CPUTYPE      CORTEX-A9 0x80090000    ;force APB Debug Base address
#0 STARTUP      HALT
#0 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#0 MEMACCESS    CORE  10                ;memory access via core (80 TCK's access delay)
#0 STEPMODE     OVER                    ;OVER or INTO
#0 BREAKMODE    HARD                    ;SOFT or HARD
#0 DCC          7                       ;DCC I/O via TCP port 7
#0 SCANPRED     0 0                     ;ARM DAP is in front
#0 SCANSUCC     1 6                     ;JTAG TAP is after

; CoreID#1 parameters
#1 CPUTYPE      CORTEX-A9 0x80092000    ;force APB Debug Base address
#1 STARTUP      HALT
#1 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#1 MEMACCESS    CORE  10                ;memory access via core (80 TCK's access delay)
#1 STEPMODE     OVER                    ;OVER or INTO
#1 BREAKMODE    HARD                    ;SOFT or HARD
#1 SCANPRED     0 0                     ;ARM DAP is in front
#1 SCANSUCC     1 6                     ;JTAG TAP is after

[HOST]
#0 PROMPT       A9#0>
#1 PROMPT       A9#1>


[FLASH]


[REGS]
FILE            $regCortex-A9.def