; ---------------------------------------
; Minimal bdiGDB configuration for Vybrid
; ---------------------------------------
;
; Commands supported in the SCANINIT and SCANPOST strings:
;
;  I<n>=<...b2b1b0>   write IR, b0 is first scanned
;  D<n>=<...b2b1b0>   write DR, b0 is first scanned
;                       n  : the number of bits 1..256
;                       bx : a data byte, two hex digits
;  W<n>               wait for n (decimal) micro seconds
;  T1                 assert TRST
;  T0                 release TRST
;  R1                 assert RESET
;  R0                 release RESET
;  CH<n>              clock TCK n (decimal) times with TMS high
;  CL<n>              clock TCK n (decimal) times with TMS low
;  M<addr>=<value>    write 32-bit to AHB
;  P<addr>=<value>    write 32-bit to Access Port register
;
;
; Low level access to CoreSight debug system:
; -------------------------------------------
; RDP   <addr>                 display Debug Port (DP) register
; RAP   <addr>                 display Access Port (AP) register
; RDBG  <nbr>  [<cnt>]         display core debug register
; WDP   <addr> <value>         modify Debug Port (DP) register
; WAP   <addr> <value>         modify Access Port (AP) register
; WDBG  <nbr>  <value>         modify core debug register
; MDAPB <addr> [<cnt>]         display APB memory
; MMAPB <addr> <value>         modify  APB memory
; MDAHB <addr> [<cnt>]         display AHB/AXI memory (32-bit)
; MMAHB <addr> <value>         modify  AHB/AXI memory (32-bit)
;


[INIT]
;


[TARGET]
POWERUP         3000            ;start delay after power-up detected in ms
CLOCK           8000000         ;JTAG clock 8 MHz
RESET           NONE            ;see SCANINIT
;
; There is no debug communication possible when RESET is asserted.
; We use the MDM-AP Control to force the cores to halt out of reset.
; Cortex-M4 is not active out of reset, we keep CM4 Halt asserted.
SCANINIT        r1:w500000:             ;assert reset
SCANINIT        p04000004=00040004:     ;MDM-AP Control: CA5 Halt, CM4 Halt
SCANINIT        r0:w100000:             ;release reset and wait
;
SCANPOST        p04000004=00000004      ;MDM-AP Control: release CA5 Halt
                                        ;use Telnet "wap 0x04000004 0" to release CM4 Halt
;
;
; CoreID#0 parameters: Cortex-A5 (active out of reset)
#0 CPUTYPE      CORTEX-A5       ;Core is Cortex-A5
#0 STARTUP      HALT            ;halt immediately, modify also SCANINIT
;#0 STARTUP      STOP 2000       ;let core run, modify also SCANINIT
;#0 STARTUP      RUN             ;let core run, modify also SCANINIT
#0 ENDIAN       LITTLE          ;memory model (LITTLE | BIG)
#0 BREAKMODE    HARD            ;SOFT or HARD
#0 MEMACCESS    CORE   10       ;memory access via Core (80 TCK's access delay)
;
; CoreID#1 parameters: Cortex-M4 (not active out of reset)
#1 CPUTYPE      CORTEX-M4  3    ;AP-Select 3
#1 STARTUP      IDLE            ;ignore until attached
#1 ENDIAN       LITTLE
#1 BREAKMODE    SOFT
#1 MEMACCESS    AHB   1         ;memory access via AHB  (8 TCK's access delay)
;
; CoreID#2 parameters: Dummy core for AHB accesses
#2 CPUTYPE      CORTEX-A5
#2 STARTUP      IDLE
#2 MEMACCESS    AHB    8
;


[HOST]
#0 PROMPT          CA5>
#1 PROMPT          CM4>
#2 PROMPT          AHB>


[FLASH]


[REGS]
#0 FILE            $regVybridCA5.def
#1 FILE            $regCortex-M4.def