; bdiGDB configuration for TI TMS570 ; ---------------------------------- ; ; Commands supported in the SCANINIT and SCANPOST strings: ; ; I=<...b2b1b0> write IR, b0 is first scanned ; D=<...b2b1b0> write DR, b0 is first scanned ; n : the number of bits 1..256 ; bx : a data byte, two hex digits ; W wait for n (decimal) micro seconds ; T1 assert TRST ; T0 release TRST ; R1 assert RESET ; R0 release RESET ; CH clock TCK n (decimal) times with TMS high ; CL clock TCK n (decimal) times with TMS low ; ; [INIT] WGPR 11 0x08000020 ;set frame pointer to free RAM WM32 0x08000020 0x08000028 ;dummy stack frame WGPR 13 0x0800fffc ;set SP to internal SRAM ; WCP15 0x4001 0x00f00000 ;CPACC: allow CP10 and CP11 access WCP10 0x00e8 0x40000000 ;FPEXC: enable VFP coprocessor ; ; Fill some code into SRAM WM32 0x08000100 0xe1a00000 ;nop WM32 0x08000104 0xe1a00000 ;nop WM32 0x08000108 0xe1a00000 ;nop WM32 0x0800010c 0xe1a00000 ;nop WM32 0x08000110 0xe1a00000 ;nop WM32 0x08000114 0xe1a00000 ;nop WM32 0x08000118 0xe1a00000 ;nop WM32 0x0800011c 0xe1a00000 ;nop WM32 0x08000120 0xe1a00000 ;nop WM32 0x08000124 0xe1a00000 ;nop WM32 0x08000128 0xe1a00000 ;nop WM32 0x0800012c 0xe1a00000 ;nop WM32 0x08000130 0xe1a00000 ;nop WM32 0x08000134 0xe1a00000 ;nop WM32 0x08000138 0xe1a00000 ;nop WM32 0x0800013c 0xeafffffb ;b 0x08000130 ; ; Test Bit manipulation ; --------------------- ; RM8
[ [ [ ; WM32 0x08000000 0x11111111 ;set initilal value RM32 0x08000000 0x10101010 ;read and XOR WMX 0xff00ff00 0x00000003 ;AND, OR and write back ; WM32 0x08000004 0xffffffff ;set initilal value RM32 0x08000004 0x00000000 ;read and XOR WMX 0x12345678 0x00000000 ;AND, OR and write back ; WM32 0x08000008 0xffffffff ;set initilal value RM32 0x08000008 0xffffffff ;read and XOR WMX 0xffffffff 0x12345678 ;AND, OR and write back ; WM32 0x0800000c 0xffffffff ;set initilal value RM8 0x0800000c 0xffffffff ;read and XOR WMX 0xffffffff 0x12345678 ;AND, OR and write back ; [TARGET] CPUTYPE CORTEX-R4 CLOCK 8000000 ;8MHz JTAG clock POWERUP 2000 ;power-up delay TRST PUSHPULL ;TRST driver type (OPENDRAIN | PUSHPULL) RESET HARD ;NONE | HARD (ms) STARTUP HALT ENDIAN BIG ;memory model (LITTLE | BIG) WAKEUP 100 VECTOR CATCH 0x00DE ;catch all vectors MEMACCESS CORE 5 ;memory access via core (40 TCK's access delay) ;MEMACCESS AHB 5 ;memory access via AHB (40 TCK's access delay) ; SCANPRED 1 6 ;count for ICEPick TAP SCANSUCC 0 0 ;no device after Cortex-A8 ; ; Configure ICEPick module to make Cortex-R4 DAP-TAP visible SCANINIT r1:t1:w1000:t0: ;assert reset and toggle TRST SCANINIT w1000:ch10:w1000: ;clock TCK with TMS high and wait SCANINIT i6=07:d8=89:i6=02: ;connect and select router SCANINIT d32=81000080: ;IP control: KeepPowered SCANINIT d32=a0002048: ;TAP0: DebugConnect, ForcePower, ForceActive SCANINIT d32=a0002148: ;enable TAP0 SCANINIT cl10:i10=ffff ;clock 10 times in RTI, scan bypass ; [HOST] FILE E:/temp/dump128k.bin FORMAT BIN 0x08000000 PROMPT TMS570> [FLASH] ; only to test helper code execution WORKSPACE 0x08001000 ;workspace at 0x08001000 CHIPTYPE S29VSRX16 CHIPSIZE 0x10000 BUSWIDTH 16 SWAP FILE E:/temp/dump16k.bin FORMAT BIN 0x08011000 [REGS] FILE $regCortex-R4.def