; ---------------------------------------
; Minimal bdiGDB configuration for Tegra2
; ---------------------------------------
;
; Out of reset only core #0 is accessible.
; Core #1 has no clock or is not even powered.
; So there is no debug access to this core possible until it
; is enabled and clocked. Therefore startup mode IDLE is used.
; You can attach this core via Telnet once it is alive.
;
;
; Commands supported in the SCANINIT and SCANPOST strings:
;
;  I<n>=<...b2b1b0>   write IR, b0 is first scanned
;  D<n>=<...b2b1b0>   write DR, b0 is first scanned
;                       n  : the number of bits 1..256
;                       bx : a data byte, two hex digits
;  W<n>               wait for n (decimal) micro seconds
;  T1                 assert TRST
;  T0                 release TRST
;  R1                 assert RESET
;  R0                 release RESET
;  CH<n>              clock TCK n (decimal) times with TMS high
;  CL<n>              clock TCK n (decimal) times with TMS low
;
;
; Low level access to CoreSight debug system:
; -------------------------------------------
; RDP   <addr>                 display Debug Port (DP) register
; RAP   <addr>                 display Access Port (AP) register
; RDBG  <nbr>  [<cnt>]         display core debug register
; WDP   <addr> <value>         modify Debug Port (DP) register
; WAP   <addr> <value>         modify Access Port (AP) register
; WDBG  <nbr>  <value>         modify core debug register
; MDAPB <addr> [<cnt>]         display APB memory
; MMAPB <addr> <value>         modify  APB memory
; MDAHB <addr> [<cnt>]         display AHB memory (32-bit)
; MMAHB <addr> <value>         modify  AHB memory (32-bit)
;


[INIT]
;
; Enable second core and let it exeute a loop
WM32    0x40001000  0xE320F000  ;nop
WM32    0x40001004  0xE320F000  ;nop
WM32    0x40001008  0xE320F000  ;nop
WM32    0x4000100c  0xE320F000  ;nop
WM32    0x40001010  0xE320F000  ;nop
WM32    0x40001014  0xE320F000  ;nop
WM32    0x40001018  0xEAFFFFFC  ;b -4
WM32    0x6000f100  0x40001000  ;set boot vector
WM32    0x6000604c  0x00000003  ;enable second core clock
WM32    0x60006344  0x00002222  ;
;

[TARGET]
POWERUP         2000                    ;start delay after power-up detected in ms
CLOCK           8000000                 ;JTAG clock 8MHz
RESET           NONE                    ;see SCANINIT
WAKEUP          500
;
SCANINIT t1:w100000:                    ;force TRST low, selects CPU JTAG
SCANINIT r1:w100000:r0:w500000:         ;toggle reset and wait
SCANINIT ch10:w1000:                    ;clock TCK with TMS high and wait
;

; CoreID#0 parameters: First Cortex-A9 core
#0 CPUTYPE      CORTEX-A9 0x80030000    ;force DBG-AP address
#0 STARTUP      HALT                    ;halt as soon as possible
#0 ENDIAN       LITTLE
#0 MEMACCESS    CORE
#0 STEPMODE     OVER
#0 BREAKMODE    HARD

; CoreID#1 parameters: Second Cortex-A9 core
#1 CPUTYPE      CORTEX-A9 0x80032000    ;force DBG-AP address
#1 STARTUP      IDLE                    ;ignore until attached
#1 ENDIAN       LITTLE
#1 MEMACCESS    CORE
#1 STEPMODE     OVER
#1 BREAKMODE    HARD

; CoreID#2 parameters: ARM7 at JTAG-AP port 0
#2 CPUTYPE      ARM7  0                 ;ARM7 connected to JTAG-AP port 0
#2 STARTUP      RUN                     ;let the AVP ARM7 core running
#2 ENDIAN       LITTLE
#2 MEMACCESS    CORE  5                 ;JTAG_AP: 40 TCK's access delay
#2 BREAKMODE    HARD
;
; CoreID#3 parameters: Dummy Cortex-A9 core for AHB accesses
#3 CPUTYPE      CORTEX-A9               ;not preset core
#3 STARTUP      IDLE                    ;ignore always
#3 ENDIAN       LITTLE
#3 MEMACCESS    AHB


[HOST]
#0 PROMPT       T2#0>
#1 PROMPT       T2#1>
#2 PROMPT       ARM7>
#3 PROMPT       AHB>


[FLASH]


[REGS]
#0 FILE         $regTegra2.def          ;default reg def
#2 FILE         $regARM7.def