; -------------------------------------------------
; Minimal bdiGDB configuration for SAMA5D3 SWD-Mode
; -------------------------------------------------
;
; Memory access via AHB/AXI is not supported.
; It seems that there is no AHB-AP / AXI-AP implemented.
;
; Note: JTAG access is disabled during the execution of ROM Code Sequence.
; It is re-enabled when jumping into SRAM when a valid code has been found
; on an external NVM, in the same time the ROM memory is hidden.
; If no valid boot has been found on an external NVM, the ROM Code enables
; the USB connection and waits for a special command to set the chip in Secure mode.
; If any other character is received, the ROM Code starts the Standard SAM-BA Monitor,
; locks access to the ROM memory and re-enables the JTAG.
;
;

[INIT]
;


[TARGET]
CLOCK           8000000         ;JTAG clock 8 MHz
;
;--- use this when JTAG gets automatically enabled ---
;POWERUP         1000            ;use it when JTAG gets automatically enabled
;RESET           NONE  500       ;toggle reset but release before SWD setup
;
;--- else enable JTAG within 20 seconds via SAM-BA Monitor ---
POWERUP         20000           ;enable JTAG within 20 seconds via SAM-BA Monitor
RESET           NONE
;
;
; CoreID#0 parameters: Cortex-A5 (active out of reset)
#0 CPUTYPE      CORTEX-A5       ;Core is Cortex-A5
#0 STARTUP      HALT            ;halt as soon as possible
;#0 STARTUP      STOP 2000       ;let core run
;#0 STARTUP      RUN             ;let core run
#0 ENDIAN       LITTLE          ;memory model (LITTLE | BIG)
#0 BREAKMODE    HARD            ;SOFT or HARD
#0 MEMACCESS    CORE   10       ;memory access via Core (80 TCK's access delay)
;

[HOST]
#0 PROMPT          SAMA5D3>


[FLASH]


[REGS]
FILE            $regCortex-A5.def