;Register definition for Cortex-A9
;=================================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CPx	CPx register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;
; CPx Registers Numbers for Cortex-A9 cores:
;
;       +-----+-+-------+-----+-+-------+
;       |opc_2|0|  CRm  |opc_1|0|  nbr  |
;       +-----+-+-------+-----+-+-------+
;
; The 16bit register number is used to build the appropriate MCR/MRC instruction.
;
;
;name		type	addr		size
;-------------------------------------------
;
;
; CP15 Registers
;
mainid		CP15    0x0000          32      ;ID code
cachetype   	CP15    0x2000          32      ;Cache type
tcmstatus       CP15    0x4000          32      ;TCM status
tlbtype         CP15    0x6000          32      ;TCM type
mputype         CP15    0x8000          32      ;MPU type
multipid        CP15    0xa000          32      ;Multiprocessor ID
;
procfeature0    CP15    0x0100          32      ;Processor Feature 0
procfeature1    CP15    0x2100          32      ;Processor Feature 1
dbgfeature0     CP15    0x4100          32      ;Debug Feature 0
auxfeature0     CP15    0x6100          32      ;Auxiliary Feature 0
memfeature0     CP15    0x8100          32      ;Memory Model Feature 0
memfeature1     CP15    0xa100          32      ;Memory Model Feature 1
memfeature2     CP15    0xc100          32      ;Memory Model Feature 2
memfeature3     CP15    0xe100          32      ;Memory Model Feature 3
;
instrattr0      CP15    0x0200          32      ;Instruction Set Attribute 0
instrattr1      CP15    0x2200          32      ;Instruction Set Attribute 1
instrattr2      CP15    0x4200          32      ;Instruction Set Attribute 2
instrattr3      CP15    0x6200          32      ;Instruction Set Attribute 3
instrattr4      CP15    0x8200          32      ;Instruction Set Attribute 4
instrattr5      CP15    0xa200          32      ;Instruction Set Attribute 5
instrattr6      CP15    0xc200          32      ;Instruction Set Attribute 6
instrattr7      CP15    0xe200          32      ;Instruction Set Attribute 7
;
control         CP15    0x0001          32      ;Control
auxcontrol     	CP15    0x2001          32      ;Auxiliary Control
cpaccess   	CP15    0x4001          32      ;Coprocessor Access
;
;securecfg       CP15    0x0101          32      ;Secure Configuration
;securedbg       CP15    0x2101          32      ;Secure Debug Enable
;nonsecure       CP15    0x4101          32      ;Nonsecure Access Control
;
ttb0            CP15    0x0002          32      ;Translation Table Base 0
ttb1            CP15    0x2002          32      ;Translation Table Base 1
ttbc            CP15    0x4002          32      ;Translation Table Base Control
;
dac             CP15    0x0003          32      ;Domain Access Control
;
dfsr     	CP15    0x0005          32      ;Data Fault Status
ifsr     	CP15    0x2005          32      ;Inst Fault Status
dauxfsr     	CP15    0x0105          32      ;Data Auxiliary Fault Status
iaucfsr     	CP15    0x2105          32      ;Inst Auxiliary Fault Status
;
dfar     	CP15    0x0006          32      ;Data Fault Address
ifar     	CP15    0x4006          32      ;Inst Fault Address
;
fcsepid        	CP15    0x000d          32      ;Process ID
context        	CP15    0x200d          32      ;Context ID
;
;
; DAP APB Registers
;
cpu0_didr       APB     0x80030000
cpu0_wfar       APB     0x80030018
cpu0_vcr        APB     0x8003001C
cpu0_dscr       APB     0x80030088
cpu0_prcr       APB     0x80030310
cpu0_prsr       APB     0x80030314
cpu0_authstatus APB     0x80030fb8
cpu0_devid      APB     0x80030fc8
cpu0_devtype    APB     0x80030fcc
;
cpu0_bvr0       APB     0x80030100
cpu0_bvr1       APB     0x80030104
cpu0_bcr0       APB     0x80030140
cpu0_bcr1       APB     0x80030144
;

