;Register definition for TI OMAP3430
;===================================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CPx	CPx register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;
; CPx Registers Numbers for Cortex-A8 cores:
;
;       +-----+-+-------+-----+-+-------+
;       |opc_2|0|  CRm  |opc_1|0|  nbr  |
;       +-----+-+-------+-----+-+-------+
;
; The 16bit register number is used to build the appropriate MCR/MRC instruction.
;
;
;name		type	addr		size
;-------------------------------------------
;
;
; CP15 Registers
;
mainid		CP15    0x0000          32      ;ID code
cachetype   	CP15    0x2000          32      ;Cache type
tcmstatus       CP15    0x4000          32      ;TCM status
tlbtype         CP15    0x6000          32      ;TCM type
mputype         CP15    0x8000          32      ;MPU type
multipid        CP15    0xa000          32      ;Multiprocessor ID
;
procfeature0    CP15    0x0100          32      ;Processor Feature 0
procfeature1    CP15    0x2100          32      ;Processor Feature 1
dbgfeature0     CP15    0x4100          32      ;Debug Feature 0
auxfeature0     CP15    0x6100          32      ;Auxiliary Feature 0
memfeature0     CP15    0x8100          32      ;Memory Model Feature 0
memfeature1     CP15    0xa100          32      ;Memory Model Feature 1
memfeature2     CP15    0xc100          32      ;Memory Model Feature 2
memfeature3     CP15    0xe100          32      ;Memory Model Feature 3
;
instrattr0      CP15    0x0200          32      ;Instruction Set Attribute 0
instrattr1      CP15    0x2200          32      ;Instruction Set Attribute 1
instrattr2      CP15    0x4200          32      ;Instruction Set Attribute 2
instrattr3      CP15    0x6200          32      ;Instruction Set Attribute 3
instrattr4      CP15    0x8200          32      ;Instruction Set Attribute 4
instrattr5      CP15    0xa200          32      ;Instruction Set Attribute 5
instrattr6      CP15    0xc200          32      ;Instruction Set Attribute 6
instrattr7      CP15    0xe200          32      ;Instruction Set Attribute 7
;
control         CP15    0x0001          32      ;Control
auxcontrol     	CP15    0x2001          32      ;Auxiliary Control
cpaccess   	CP15    0x4001          32      ;Coprocessor Access
;
;securecfg       CP15    0x0101          32      ;Secure Configuration
;securedbg       CP15    0x2101          32      ;Secure Debug Enable
;nonsecure       CP15    0x4101          32      ;Nonsecure Access Control
;
ttb0            CP15    0x0002          32      ;Translation Table Base 0
ttb1            CP15    0x2002          32      ;Translation Table Base 1
ttbc            CP15    0x4002          32      ;Translation Table Base Control
;
dac             CP15    0x0003          32      ;Domain Access Control
;
dfsr     	CP15    0x0005          32      ;Data Fault Status
ifsr     	CP15    0x2005          32      ;Inst Fault Status
dauxfsr     	CP15    0x0105          32      ;Data Auxiliary Fault Status
iaucfsr     	CP15    0x2105          32      ;Inst Auxiliary Fault Status
;
dfar     	CP15    0x0006          32      ;Data Fault Address
ifar     	CP15    0x4006          32      ;Inst Fault Address
;
fcsepid        	CP15    0x000d          32      ;Process ID
context        	CP15    0x200d          32      ;Context ID
;
;
; L1 system array access
;ddata0          CP15    0x000f          32      ;Data Level 1 data 0
;ddata1          CP15    0x200f          32      ;Data Level 1 data 1
;idata0          CP15    0x010f          32      ;Inst Level 1 data 0
;idata1          CP15    0x210f          32      ;Inst Level 1 data 1
;
;dtagread        CP15    0xc20f          32      ;D-TAG  read
;ddataread       CP15    0xe20f          32      ;D-DATA read
;itagread        CP15    0xc30f          32      ;I-TAG  read
;idataread       CP15    0xe30f          32      ;I-DATA read
;
;
; DAP APB Registers
;
dap_pc_fer      APB     0xd401d030              ;DAP_PC for Ferrari
dap_pc_ime      APB     0xd401d034              ;DAP_PC for IME
dap_pc_ilf      APB     0xd401d038              ;DAP_PC for ILF
dap_pc_vlc      APB     0xd401d03c              ;DAP_PC for VLC
dap_pc_core     APB     0xd401d040              ;DAP_PC for Core
;
dscr            APB     0xd4011088
prcr            APB     0xd4011310
prsr            APB     0xd4011314
authstatus      APB     0xd4011fb8
devid           APB     0xd4011fc8
devtype         APB     0xd4011fcc
;
decs_version    APB     0xd4012000              ;TI debug extender CS
decs_dccr       APB     0xd4012004
decs_dcsr       APB     0xd4012008
decs_tcr        APB     0xd4012010
decs_rcsr       APB     0xd4012014
decs_icsr       APB     0xd4012020
decs_dcon       APB     0xd40120fc
;
;
; Watchdog Timer WDT1
;
widr            MM      0x48314000
wd_sysconfig    MM      0x48314010
wd_sysstatus    MM      0x48314014
wisr            MM      0x48314018
wier            MM      0x4831401c
wclr            MM      0x48314024
wccr            MM      0x48314028
wldr            MM      0x4831402c
widr            MM      0x48314030
wwps            MM      0x48314034
wspr            MM      0x48314048
;