;Register definition for Cortex-A9
;=================================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CPx	CPx register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;
; CPx Registers Numbers for Cortex-A9 cores:
;
;       +-----+-+-------+-----+-+-------+
;       |opc_2|0|  CRm  |opc_1|0|  nbr  |
;       +-----+-+-------+-----+-+-------+
;
; The 16bit register number is used to build the appropriate MCR/MRC instruction.
;
; MRC <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>}
; DBGDSCRint:     0,           c0,    c1,      0      ==>> 0x0100
; DBGDSCRext:     0,           c0,    c2,      2      ==>> 0x4200
;
;
;name		type	addr		size
;-------------------------------------------
;
;
; CP15 Registers
;
mainid		CP15    0x0000          32      ;ID code
cachetype   	CP15    0x2000          32      ;Cache type
tcmstatus       CP15    0x4000          32      ;TCM status
tlbtype         CP15    0x6000          32      ;TCM type
mputype         CP15    0x8000          32      ;MPU type
multipid        CP15    0xa000          32      ;Multiprocessor ID
;
procfeature0    CP15    0x0100          32      ;Processor Feature 0
procfeature1    CP15    0x2100          32      ;Processor Feature 1
dbgfeature0     CP15    0x4100          32      ;Debug Feature 0
auxfeature0     CP15    0x6100          32      ;Auxiliary Feature 0
memfeature0     CP15    0x8100          32      ;Memory Model Feature 0
memfeature1     CP15    0xa100          32      ;Memory Model Feature 1
memfeature2     CP15    0xc100          32      ;Memory Model Feature 2
memfeature3     CP15    0xe100          32      ;Memory Model Feature 3
;
instrattr0      CP15    0x0200          32      ;Instruction Set Attribute 0
instrattr1      CP15    0x2200          32      ;Instruction Set Attribute 1
instrattr2      CP15    0x4200          32      ;Instruction Set Attribute 2
instrattr3      CP15    0x6200          32      ;Instruction Set Attribute 3
instrattr4      CP15    0x8200          32      ;Instruction Set Attribute 4
instrattr5      CP15    0xa200          32      ;Instruction Set Attribute 5
instrattr6      CP15    0xc200          32      ;Instruction Set Attribute 6
instrattr7      CP15    0xe200          32      ;Instruction Set Attribute 7
;
control         CP15    0x0001          32      ;Control
auxcontrol     	CP15    0x2001          32      ;Auxiliary Control
cpaccess   	CP15    0x4001          32      ;Coprocessor Access
;
securecfg       CP15    0x0101          32      ;Secure Configuration
securedbg       CP15    0x2101          32      ;Secure Debug Enable
nonsecure       CP15    0x4101          32      ;Nonsecure Access Control
;
ttb0            CP15    0x0002          32      ;Translation Table Base 0
ttb1            CP15    0x2002          32      ;Translation Table Base 1
ttbc            CP15    0x4002          32      ;Translation Table Base Control
;
dac             CP15    0x0003          32      ;Domain Access Control
;
dfsr     	CP15    0x0005          32      ;Data Fault Status
ifsr     	CP15    0x2005          32      ;Inst Fault Status
dauxfsr     	CP15    0x0105          32      ;Data Auxiliary Fault Status
iaucfsr     	CP15    0x2105          32      ;Inst Auxiliary Fault Status
;
dfar     	CP15    0x0006          32      ;Data Fault Address
ifar     	CP15    0x4006          32      ;Inst Fault Address
;
fcsepid        	CP15    0x000d          32      ;Process ID
context        	CP15    0x200d          32      ;Context ID
;
;
;       Device Configuration and Pin Control
dcfg_porsr1     MM      0x01EE0000      32  SWAP
dcfg_porsr2     MM      0x01EE0004      32  SWAP
dcfg_gpporcr1   MM      0x01EE0020      32  SWAP
dcfg_fusesr     MM      0x01EE0028      32  SWAP
dcfg_devdisr1   MM      0x01EE0070      32  SWAP
dcfg_devdisr2   MM      0x01EE0074      32  SWAP
dcfg_devdisr3   MM      0x01EE0078      32  SWAP
dcfg_devdisr4   MM      0x01EE007C      32  SWAP
dcfg_devdisr5   MM      0x01EE0080      32  SWAP
dcfg_coredisr   MM      0x01EE0094      32  SWAP
dcfg_svr        MM      0x01EE00A4      32  SWAP
dcfg_rstcr      MM      0x01EE00B0      32  SWAP
dcfg_rstrqpblsr MM      0x01EE00B4      32  SWAP
dcfg_rstrqmr1   MM      0x01EE00C0      32  SWAP
dcfg_rstrqsr1   MM      0x01EE00C8      32  SWAP
dcfg_brr        MM      0x01EE00E4      32  SWAP
dcfg_rcwsr1     MM      0x01EE0100      32  SWAP
dcfg_rcwsr2     MM      0x01EE0104      32  SWAP
dcfg_rcwsr3     MM      0x01EE0108      32  SWAP
dcfg_rcwsr4     MM      0x01EE010C      32  SWAP
dcfg_rcwsr5     MM      0x01EE0110      32  SWAP
dcfg_rcwsr6     MM      0x01EE0114      32  SWAP
dcfg_rcwsr7     MM      0x01EE0118      32  SWAP
dcfg_rcwsr8     MM      0x01EE011C      32  SWAP
dcfg_rcwsr9     MM      0x01EE0120      32  SWAP
dcfg_rcwsr10    MM      0x01EE0124      32  SWAP
dcfg_rcwsr11    MM      0x01EE0128      32  SWAP
dcfg_rcwsr12    MM      0x01EE012C      32  SWAP
dcfg_rcwsr13    MM      0x01EE0130      32  SWAP
dcfg_rcwsr14    MM      0x01EE0134      32  SWAP
dcfg_rcwsr15    MM      0x01EE0138      32  SWAP
dcfg_rcwsr16    MM      0x01EE013C      32  SWAP
dcfg_crstsr     MM      0x01EE0400      32  SWAP
;
scratchrw1      MM      0x01EE0200      32  SWAP
scratchrw2      MM      0x01EE0204      32  SWAP
scratchrw3      MM      0x01EE0208      32  SWAP
scratchrw4      MM      0x01EE020C      32  SWAP
scratchw1r1     MM      0x01EE0300      32  SWAP
scratchw1r2     MM      0x01EE0304      32  SWAP
scratchw1r3     MM      0x01EE0308      32  SWAP
scratchw1r4     MM      0x01EE030C      32  SWAP
;
;       Integrated Flash Controller
ifc_rev         MM      0x01530000      32  SWAP
ifc_cspr0_ext   MM      0x0153000C      32  SWAP
ifc_cspr0       MM      0x01530010      32  SWAP
ifc_cspr1_ext   MM      0x01530018      32  SWAP
ifc_cspr1       MM      0x0153001C      32  SWAP
ifc_cspr2_ext   MM      0x01530024      32  SWAP
ifc_cspr2       MM      0x01530028      32  SWAP
ifc_cspr3_ext   MM      0x01530030      32  SWAP
ifc_cspr3       MM      0x01530034      32  SWAP
ifc_cspr4_ext   MM      0x0153003C      32  SWAP
ifc_cspr4       MM      0x01530040      32  SWAP
ifc_cspr5_ext   MM      0x01530048      32  SWAP
ifc_cspr5       MM      0x0153004C      32  SWAP
ifc_cspr6_ext   MM      0x01530054      32  SWAP
ifc_cspr6       MM      0x01530058      32  SWAP
;
ifc_amask0      MM      0x015300A0      32  SWAP
ifc_amask1      MM      0x015300AC      32  SWAP
ifc_amask2      MM      0x015300B8      32  SWAP
ifc_amask3      MM      0x015300C4      32  SWAP
ifc_amask4      MM      0x015300D0      32  SWAP
ifc_amask5      MM      0x015300DC      32  SWAP
ifc_amask6      MM      0x015300E8      32  SWAP
;
ifc_csor0       MM      0x01530130      32  SWAP
ifc_csor0_ext   MM      0x01530134      32  SWAP
ifc_csor1       MM      0x0153013C      32  SWAP
ifc_csor1_ext   MM      0x01530140      32  SWAP
ifc_csor2       MM      0x01530148      32  SWAP
ifc_csor2_ext   MM      0x0153014C      32  SWAP
ifc_csor3       MM      0x01530154      32  SWAP
ifc_csor3_ext   MM      0x01530158      32  SWAP
ifc_csor4       MM      0x01530160      32  SWAP
ifc_csor4_ext   MM      0x01530164      32  SWAP
ifc_csor5       MM      0x0153016C      32  SWAP
ifc_csor5_ext   MM      0x01530170      32  SWAP
ifc_csor6       MM      0x01530178      32  SWAP
ifc_csor6_ext   MM      0x0153017C      32  SWAP
;
ifc_ftim0_cs0   MM      0x015301C0      32  SWAP
ifc_ftim1_cs0   MM      0x015301C4      32  SWAP
ifc_ftim2_cs0   MM      0x015301C8      32  SWAP
ifc_ftim3_cs0   MM      0x015301CC      32  SWAP
ifc_ftim0_cs1   MM      0x015301F0      32  SWAP
ifc_ftim1_cs1   MM      0x015301F4      32  SWAP
ifc_ftim2_cs1   MM      0x015301F8      32  SWAP
ifc_ftim3_cs1   MM      0x015301FC      32  SWAP
ifc_ftim0_cs2   MM      0x01530220      32  SWAP
ifc_ftim1_cs2   MM      0x01530224      32  SWAP
ifc_ftim2_cs2   MM      0x01530228      32  SWAP
ifc_ftim3_cs2   MM      0x0153022C      32  SWAP
ifc_ftim0_cs3   MM      0x01530250      32  SWAP
ifc_ftim1_cs3   MM      0x01530254      32  SWAP
ifc_ftim2_cs3   MM      0x01530258      32  SWAP
ifc_ftim3_cs3   MM      0x0153025C      32  SWAP
ifc_ftim0_cs4   MM      0x01530280      32  SWAP
ifc_ftim1_cs4   MM      0x01530284      32  SWAP
ifc_ftim2_cs4   MM      0x01530288      32  SWAP
ifc_ftim3_cs4   MM      0x0153028C      32  SWAP
ifc_ftim0_cs5   MM      0x015302B0      32  SWAP
ifc_ftim1_cs5   MM      0x015302B4      32  SWAP
ifc_ftim2_cs5   MM      0x015302B8      32  SWAP
ifc_ftim3_cs5   MM      0x015302BC      32  SWAP
ifc_ftim0_cs6   MM      0x015302E0      32  SWAP
ifc_ftim1_cs6   MM      0x015302E4      32  SWAP
ifc_ftim2_cs6   MM      0x015302E8      32  SWAP
ifc_ftim3_cs6   MM      0x015302EC      32  SWAP
;
ifc_rb_stat     MM      0x01530400      32  SWAP
ifc_gcr         MM      0x0153040C      32  SWAP
ifc_cm_ee_stat  MM      0x01530418      32  SWAP
ifc_cm_evter_en MM      0x01530424      32  SWAP
ifc_cm_evter_ie MM      0x01530430      32  SWAP
ifc_cm_erattr0  MM      0x0153043C      32  SWAP
ifc_cm_erattr1  MM      0x01530440      32  SWAP
ifc_ccr         MM      0x0153044C      32  SWAP
ifc_csr         MM      0x01530450      32  SWAP
ifc_ddr_ccr_low MM      0x01530454      32  SWAP
ifc_gpcm_ee_sta MM      0x01530800      32  SWAP
ifc_gpcm_ee_en  MM      0x0153080C      32  SWAP
ifc_gpcm_ee_ien MM      0x01530818      32  SWAP
ifc_gpcm_eratt0 MM      0x01530824      32  SWAP
ifc_gpcm_eratt1 MM      0x01530828      32  SWAP
ifc_gpcm_eratt2 MM      0x0153082C      32  SWAP
ifc_gpcm_stat   MM      0x01530830      32  SWAP
;
ifc_ncfgr       MM      0x01531000      32  SWAP
ifc_nand_fcr0   MM      0x01531014      32  SWAP
ifc_nand_fcr1   MM      0x01531018      32  SWAP
ifc_row0        MM      0x0153103C      32  SWAP
ifc_col0        MM      0x01531044      32  SWAP
ifc_col0_2kb    MM      0x01531044      32  SWAP
ifc_col0_4kb    MM      0x01531044      32  SWAP
ifc_col0_8kb    MM      0x01531044      32  SWAP
ifc_row1        MM      0x0153104C      32  SWAP
ifc_col1        MM      0x01531054      32  SWAP
ifc_col1_2kb    MM      0x01531054      32  SWAP
ifc_col1_4kb    MM      0x01531054      32  SWAP
ifc_col1_8kb    MM      0x01531054      32  SWAP
ifc_row2        MM      0x0153105C      32  SWAP
ifc_col2        MM      0x01531064      32  SWAP
ifc_col2_2kb    MM      0x01531064      32  SWAP
ifc_col2_4kb    MM      0x01531064      32  SWAP
ifc_col2_8kb    MM      0x01531064      32  SWAP
ifc_row3        MM      0x0153106C      32  SWAP
ifc_col3        MM      0x01531074      32  SWAP
ifc_col3_2kb    MM      0x01531074      32  SWAP
ifc_col3_4kb    MM      0x01531074      32  SWAP
ifc_col3_8kb    MM      0x01531074      32  SWAP
ifc_nand_bc     MM      0x01531108      32  SWAP
ifc_nand_fir0   MM      0x01531110      32  SWAP
ifc_nand_fir1   MM      0x01531114      32  SWAP
ifc_nand_fir2   MM      0x01531118      32  SWAP
ifc_nand_csel   MM      0x0153115C      32  SWAP
ifc_nandseq_str MM      0x01531164      32  SWAP
ifc_nand_ee_sta MM      0x0153116C      32  SWAP
ifc_pgrdcmpl_es MM      0x01531174      32  SWAP
ifc_nand_ee_en  MM      0x01531180      32  SWAP
ifc_nand_ee_ien MM      0x0153118C      32  SWAP
ifc_nand_eratt0 MM      0x01531198      32  SWAP
ifc_nand_eratt1 MM      0x0153119C      32  SWAP
ifc_nand_fsr    MM      0x015311E0      32  SWAP
ifc_eccstat0    MM      0x015311E8      32  SWAP
ifc_eccstat1    MM      0x015311EC      32  SWAP
ifc_eccstat2    MM      0x015311F0      32  SWAP
ifc_eccstat3    MM      0x015311F4      32  SWAP
ifc_nandcr      MM      0x01531278      32  SWAP
ifc_nand_ab_trg MM      0x01531284      32  SWAP
ifc_nand_mdr    MM      0x0153128C      32  SWAP
ifc_nor_ee_stat MM      0x01531400      32  SWAP
ifc_nor_ee_en   MM      0x0153140C      32  SWAP
ifc_nor_ee_ien  MM      0x01531418      32  SWAP
ifc_nor_eratt0  MM      0x01531424      32  SWAP
ifc_nor_eratt1  MM      0x01531428      32  SWAP
ifc_nor_eratt2  MM      0x0153142C      32  SWAP
ifc_norcr       MM      0x01531440      32  SWAP
;

