;Register definition for ARM Cortex-M4
;=====================================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;
;name		type	addr		size
;-------------------------------------------
;
sp_main         GPR     17              32      ;Main Stackpointer
sp_process      GPR     18              32      ;Process Stackpointer
ctr_fm_bp_pm    GPR     20              32      ;Control,FaultMask,BasePri,PriMask
fpscr           GPR     33              32      ;Floating-Point Status and Control Register
;
; FP registers S0 - S31
fpr_s0          GPR     64              32
fpr_s1          GPR     65              32
fpr_s2          GPR     66              32
fpr_s3          GPR     67              32
fpr_s4          GPR     68              32
fpr_s5          GPR     69              32
fpr_s6          GPR     70              32
fpr_s7          GPR     71              32
fpr_s8          GPR     72              32
fpr_s9          GPR     73              32
fpr_s10         GPR     74              32
fpr_s11         GPR     75              32
fpr_s12         GPR     76              32
fpr_s13         GPR     77              32
fpr_s14         GPR     78              32
fpr_s15         GPR     79              32
fpr_s16         GPR     80              32
fpr_s17         GPR     81              32
fpr_s18         GPR     82              32
fpr_s19         GPR     83              32
fpr_s20         GPR     84              32
fpr_s21         GPR     85              32
fpr_s22         GPR     86              32
fpr_s23         GPR     87              32
fpr_s24         GPR     88              32
fpr_s25         GPR     89              32
fpr_s26         GPR     90              32
fpr_s27         GPR     91              32
fpr_s28         GPR     92              32
fpr_s29         GPR     93              32
fpr_s30         GPR     94              32
fpr_s31         GPR     95              32
;
fpdscr          MM      0xE000EF3C      32      ;FP Default Status Control Register
fpccr           MM      0xE000EF34      32      ;FP Context Control Register
fpcar           MM      0xE000EF38      32      ;FP Context Address Register
fpdscr          MM      0xE000EF3C      32      ;FP Default Status Control Register
mvfr0           MM      0xE000EF40      32      ;Media and VFP Feature Register 0, MVFR0
mvfr1           MM      0xE000EF44      32      ;Media and VFP Feature Register 1, MVFR1
;
; System control and ID registers
cpuid           MM      0xE000ED00      32      ;CPUID Base Register
icsr            MM      0xE000ED04      32      ;Interrupt Control and State Register
vtor            MM      0xE000ED08      32      ;Vector Table Offset Register
aircr           MM      0xE000ED0C      32      ;Application Interrupt and Reset Control Register
scr             MM      0xE000ED10      32      ;System Control Register
ccr             MM      0xE000ED14      32      ;Configuration and Control Register
shpr1           MM      0xE000ED18      32      ;System Handler Priority Register 1
shpr2           MM      0xE000ED1C      32      ;System Handler Priority Register 2
shpr3           MM      0xE000ED20      32      ;System Handler Priority Register 3
shcsr           MM      0xE000ED24      32      ;System Handler Control and State Register
cfsr            MM      0xE000ED28      32      ;Configurable Fault Status Register
hfsr            MM      0xE000ED2C      32      ;HardFault Status Register
dfsr            MM      0xE000ED30      32      ;Debug Fault Status Register
mmfar           MM      0xE000ED34      32      ;MemManage Fault Address Register
bfar            MM      0xE000ED38      32      ;BusFault Address Register
afsr            MM      0xE000ED3C      32      ;Auxiliary Fault Status Register
cpacr           MM      0xE000ED88      32      ;Coprocessor Access Control Register
;
; Core debug registres
dhcsr           MM      0xE000EDF0      32      ;Debugging Halting Control and Status
dcrsr           MM      0xE000EDF4      32      ;Debug Core Register Selector
dcrdr           MM      0xE000EDF8      32      ;Debug Core Register Data
demcr           MM      0xE000EDFC      32      ;Debug Core Register Selector
dfsr            MM      0xE000ED30      32      ;Debug Fault Status
;
; System debug registres
fp_ctrl         MM      0xE0002000      32      ;Flash Patch Control
fp_remap        MM      0xE0002004      32      ;Flash Patch Remap
fp_comp0        MM      0xE0002008      32      ;Flash Patch Comparator
fp_comp1        MM      0xE000200C      32      ;Flash Patch Comparator
fp_comp2        MM      0xE0002010      32      ;Flash Patch Comparator
fp_comp3        MM      0xE0002014      32      ;Flash Patch Comparator
fp_comp4        MM      0xE0002018      32      ;Flash Patch Comparator
fp_comp5        MM      0xE000201C      32      ;Flash Patch Comparator
fp_comp6        MM      0xE0002020      32      ;Flash Patch Comparator
fp_comp7        MM      0xE0002024      32      ;Flash Patch Comparator
;
dwt_ctrl        MM      0xE0001000      32      ;DWT Control
dwt_cyccnt      MM      0xE0001004      32      ;DWT Current PC Sampler Count
dwt_cpicnt      MM      0xE0001008      32      ;DWT Current CPI Count
dwt_exccnt      MM      0xE000100C      32      ;DWT Current Interrupt Overhead Count
dwt_sleepcnt    MM      0xE0001010      32      ;DWT Current Sleep Count
dwt_lsucnt      MM      0xE0001014      32      ;DWT Current LSU Count
dwt_foldcnt     MM      0xE0001018      32      ;DWT Current Fold Count
dwt_pcsr        MM      0xE000101C      32      ;DWT PC Sample
dwt_comp0       MM      0xE0001020      32      ;DWT Comparator
dwt_mask0       MM      0xE0001024      32      ;DWT Mask
dwt_function0   MM      0xE0001028      32      ;DWT Function
dwt_comp1       MM      0xE0001030      32      ;DWT Comparator
dwt_mask1       MM      0xE0001034      32      ;DWT Mask
dwt_function1   MM      0xE0001038      32      ;DWT Function
dwt_comp2       MM      0xE0001040      32      ;DWT Comparator
dwt_mask2       MM      0xE0001044      32      ;DWT Mask
dwt_function2   MM      0xE0001048      32      ;DWT Function
dwt_comp3       MM      0xE0001050      32      ;DWT Comparator
dwt_mask3       MM      0xE0001054      32      ;DWT Mask
dwt_function3   MM      0xE0001058      32      ;DWT Function
;
swo1            MM      0xE0000000      8       ;ITM 1 Byte Stimulus 0
swo2            MM      0xE0000000      16      ;ITM 2 Byte Stimulus 0
swo4            MM      0xE0000000      32      ;ITM 4 Byte Stimulus 0
itm_stimulus0   MM      0xE0000000      32      ;ITM Stimulus Ports 0-31
itm_stimulus1   MM      0xE0000004      32
itm_stimulus2   MM      0xE0000008      32
itm_stimulus3   MM      0xE000000C      32
itm_stimulus4   MM      0xE0000010      32
itm_stimulus5   MM      0xE0000014      32
itm_stimulus6   MM      0xE0000018      32
itm_stimulus7   MM      0xE000001C      32
itm_stimulus8   MM      0xE0000020      32
itm_stimulus9   MM      0xE0000024      32
itm_stimulus10  MM      0xE0000028      32
itm_stimulus11  MM      0xE000002C      32
itm_stimulus12  MM      0xE0000030      32
itm_stimulus13  MM      0xE0000034      32
itm_stimulus14  MM      0xE0000038      32
itm_stimulus15  MM      0xE000003C      32
itm_stimulus16  MM      0xE0000040      32
itm_stimulus17  MM      0xE0000044      32
itm_stimulus18  MM      0xE0000048      32
itm_stimulus19  MM      0xE000004C      32
itm_stimulus20  MM      0xE0000050      32
itm_stimulus21  MM      0xE0000054      32
itm_stimulus22  MM      0xE0000058      32
itm_stimulus23  MM      0xE000005C      32
itm_stimulus24  MM      0xE0000060      32
itm_stimulus25  MM      0xE0000064      32
itm_stimulus26  MM      0xE0000068      32
itm_stimulus27  MM      0xE000006C      32
itm_stimulus28  MM      0xE0000070      32
itm_stimulus29  MM      0xE0000074      32
itm_stimulus30  MM      0xE0000078      32
itm_stimulus31  MM      0xE000007C      32
itm_trace_ena   MM      0xE0000E00      32      ;ITM Trace Enable
itm_trace_priv  MM      0xE0000E40      32      ;ITM Trace Privilege
itm_trace_ctrl  MM      0xE0000E80      32      ;ITM Trace Control
itm_lock_access MM      0xE0000FB0      32      ;ITM Lock Access
itm_lock_status MM      0xE0000FB4      32      ;ITM Lock Status
;
;tpiu_size_supp  MM      0xE0040000      32      ;TPIU Supported Sync Port Sizes
;tpiu_size_curr  MM      0xE0040004      32      ;TPIU Current Sync Port Size
;tpiu_prescaler  MM      0xE0040010      32      ;TPIU Async Clock Prescaler
;tpiu_protocol   MM      0xE00400F0      32      ;TPIU Selected Pin Protocol
;tpiu_ff_status  MM      0xE0040300      32      ;TPIU Formatter and Flush Status
;tpiu_ff_control MM      0xE0040304      32      ;TPIU Formatter and Flush Control
;


