; bdiGDB configuration for TI OMAP5 Board
; ---------------------------------------
;
; The TI debug connector on the board does not match the
; 14-pin Embedded ICE connector. So the cable delivered
; with the BDI needs to be modified.
;
; This configuration was used to test cross-triggering via CTI.
; Once the BDI gets control, it disables MMU, caches and interrupts.
; Then it loads some simple code into OCM and lets the PC
; of all cores point to this code. The code increments r0 and this is
; used to check if the cores are really halted and restarted synchronously.
;
;
[INIT]
#0 WREG sctlr           0x00000000      ;disable MMU and Caches
#1 WREG sctlr           0x00000000      ;disable MMU and Caches
;
#0 WREG cpsr            0x000001d3      ;disable interrupt
#1 WREG cpsr            0x000001d3      ;disable interrupt
;
; Fill some A32 code into SRAM
WM32    0x40300100      0xe1a00000      ;nop
WM32    0x40300104      0xe1a00000      ;nop
WM32    0x40300108      0xe1a00000      ;nop
WM32    0x4030010c      0xe1a00000      ;nop
WM32    0x40300110      0xe1a00000      ;nop
WM32    0x40300114      0xe1a00000      ;nop
WM32    0x40300118      0xe1a00000      ;nop
WM32    0x4030011c      0xe1a00000      ;nop
WM32    0x40300120      0xe1a00000      ;nop
WM32    0x40300124      0xe1a00000      ;nop
WM32    0x40300128      0xe1a00000      ;nop
WM32    0x4030012c      0xe1a00000      ;nop
WM32    0x40300130      0xe1a00000      ;nop
WM32    0x40300134      0xe2800001      ;add	r0, r0, #1
WM32    0x40300138      0xe1a00000      ;nop
WM32    0x4030013c      0xeafffffb      ;b 0x40300130
;
#0 WREG pc              0x40300100      ;set pc to test code
#1 WREG pc              0x40300100      ;set pc to test code
;
#0 WGPR 0               0x00000000      ;clear GPR0
#1 WGPR 0               0x00000000      ;clear GPR0
;


[TARGET]
; common parameters
CLOCK           8000000                 ;JTAG clock
POWERUP         2000                    ;power-up delay
TRST            PUSHPULL                ;TRST driver type (OPENDRAIN | PUSHPULL)
WAKEUP          100                     ;delay after reset released
RESET	        NONE                    ;reset is not routed to the TI debug connector

; Force a System Warm Reset via ICEPick module
SCANINIT    t1:w1000:t0:w1000:          ;toggle TRST
SCANINIT    ch10:w1000:                 ;clock TCK with TMS high and wait
SCANINIT    i6=07:d8=89:i6=02:          ;connect and select router
SCANINIT    d32=81000081:w200000:       ;IP control: KeepPowered, SysReset

; Configure ICEPick module to make DAP-TAP visible
SCANINIT    t1:w1000:t0:w1000:          ;toggle TRST
SCANINIT    ch10:w1000:                 ;clock TCK with TMS high and wait
SCANINIT    i6=07:d8=89:i6=02:          ;connect and select router
SCANINIT    d32=81000080:               ;IP control: KeepPowered
SCANINIT    d32=af002008:               ;TAP15: DebugConnect, ForceActive
SCANINIT    d32=e0002008:               ;non_JTAG debug core#0: DebugConnect, ForceActive
SCANINIT    d32=af002108:               ;enable TAP15
SCANINIT    cl10:i10=ffff               ;clock 10 times in RTI, scan bypass

; CoreID#0 parameters (active core after reset)
#0 CPUTYPE      CORTEX-A15 0xD4140000   ;force APB Debug Base address
#0 CTI          0xD4148000 0x03         ;CTI base address and core group master
#0 DAPPC        0xD4159008              ;Cortex-A15#0 DAP-PC address
#0 STARTUP      HALT
#0 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#0 MEMACCESS    CORE  10                ;memory access via core (8 TCK's access delay)
#0 STEPMODE     OVER                    ;OVER or INTO
#0 BREAKMODE    HARD                    ;SOFT or HARD
#0 SCANPRED     1 6                     ;count for ICEPick TAP
#0 SCANSUCC     0 0                     ;no device after DAP

; CoreID#1 parameters
#1 CPUTYPE      CORTEX-A15 0xD4142000   ;force APB Debug Base address
#1 CTI          0xD4149000 0x02         ;CTI base address and core group slave
#1 DAPPC        0xD415900C              ;Cortex-A15#1 DAP-PC address
#1 STARTUP      HALT
#1 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#1 MEMACCESS    CORE  10                ;memory access via core (8 TCK's access delay)
#1 STEPMODE     OVER                    ;OVER or INTO
#1 BREAKMODE    HARD                    ;SOFT or HARD
#1 SCANPRED     1 6                     ;count for ICEPick TAP
#1 SCANSUCC     0 0                     ;no device after DAP

; CoreID#2 parameters: Dummy core for AXI accesses
#2 CPUTYPE      CORTEX-A15
#2 STARTUP      IDLE
#2 MEMACCESS    AXI    8
#2 SCANPRED     1 6                     ;count for ICEPick TAP
#2 SCANSUCC     0 0                     ;no device after DAP
;


[HOST]
#0 PROMPT      OMAP5#0>
#1 PROMPT      OMAP5#1>
#2 PROMPT          AXI>


[FLASH]


[REGS]
FILE	$regOMAP5.def