; bdiGDB configuration for Cortex-M4 in OMAP5
; -------------------------------------------
;
;
[INIT]


[TARGET]
; common parameters
CLOCK           8000000                 ;JTAG clock
POWERUP         2000                    ;power-up delay
TRST            PUSHPULL                ;TRST driver type (OPENDRAIN | PUSHPULL)
WAKEUP          100                     ;delay after reset released
RESET	        NONE                    ;reset is not routed to the TI debug connector

; Force a System Warm Reset via ICEPick module
SCANINIT    t1:w1000:t0:w1000:          ;toggle TRST
SCANINIT    ch10:w1000:                 ;clock TCK with TMS high and wait
SCANINIT    i6=07:d8=89:i6=02:          ;connect and select router
;SCANINIT    d32=81000081:w200000:       ;IP control: KeepPowered, SysReset
;
; Configure ICEPick module to make DAP-TAP visible
SCANINIT    t1:w1000:t0:w1000:          ;toggle TRST
SCANINIT    ch10:w1000:                 ;clock TCK with TMS high and wait
SCANINIT    i6=07:d8=89:i6=02:          ;connect and select router
SCANINIT    d32=81000080:               ;IP control: KeepPowered
SCANINIT    d32=a4002008:               ;TAP4: DebugConnect, ForceActive
SCANINIT    d32=a5002008:               ;TAP5: DebugConnect, ForceActive
SCANINIT    d32=a4002108:cl10:          ;enable TAP4, clock 10 times in RTI
SCANINIT    d32=a5002108:cl10:          ;enable TAP5, clock 10 times in RTI
SCANINIT    i14=ffff                    ;scan bypass

; CoreID#0 parameters: IPU_C0 Cortex-M4
#0 CPUTYPE      CORTEX-M4
#0 STARTUP      WAIT                    ;halt after released from reset
#0 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#0 MEMACCESS    AHB   2                 ;memory access via AHB  (16 TCK's access delay)
#0 STEPMODE     OVER                    ;OVER or INTO
#0 BREAKMODE    HARD                    ;SOFT or HARD
#0 SCANPRED     1 6                     ;count for ICEPick TAP
#0 SCANSUCC     1 4                     ;count for second Cortex-M4

; CoreID#0 parameters: IPU_C1 Cortex-M4
#1 CPUTYPE      CORTEX-M4
#1 STARTUP      WAIT                    ;halt after released from reset
#1 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#1 MEMACCESS    AHB   2                 ;memory access via AHB  (16 TCK's access delay)
#1 STEPMODE     OVER                    ;OVER or INTO
#1 BREAKMODE    HARD                    ;SOFT or HARD
#1 SCANPRED     2 10                    ;count for ICEPick TAP and first Cortex-M4
#1 SCANSUCC     0 0                     ;no device after this TAP


[HOST]
#0 PROMPT      M4#0>
#1 PROMPT      M4#1>


[FLASH]


[REGS]
FILE	$regCortex-M4.def