; bdiGDB configuration for TI OMAP5 Board
; ---------------------------------------
;
; This configuration allows to access all Cortex-A15 and Cortex-M4 cores.
; The Cortex-M4 are held in reset until released by code running on the A15.
; We use STARTUP WAIT, as soon as released the M4 are halted at the reset vector.
; Use STARTUP RUN if you don't want to halt the M4 immediatelly.
;
[INIT]


[TARGET]
; common parameters
CLOCK           8000000                 ;JTAG clock
POWERUP         2000                    ;power-up delay
TRST            PUSHPULL                ;TRST driver type (OPENDRAIN | PUSHPULL)
WAKEUP          100                     ;delay after reset released
RESET	        NONE                    ;reset is not routed to the TI debug connector

; Force a System Warm Reset via ICEPick module
SCANINIT    t1:w1000:t0:w1000:          ;toggle TRST
SCANINIT    ch10:w1000:                 ;clock TCK with TMS high and wait
SCANINIT    i6=07:d8=89:i6=02:          ;connect and select router
;SCANINIT    d32=81000081:w200000:       ;IP control: KeepPowered, SysReset
;
; Configure ICEPick module to make DAP-TAP visible
SCANINIT    t1:w1000:t0:w1000:          ;toggle TRST
SCANINIT    ch10:w1000:                 ;clock TCK with TMS high and wait
SCANINIT    i6=07:d8=89:i6=02:          ;connect and select router
SCANINIT    d32=81000080:               ;IP control: KeepPowered
SCANINIT    d32=af002008:               ;TAP15: DebugConnect, ForceActive
SCANINIT    d32=e0002008:               ;non_JTAG debug core#0: DebugConnect, ForceActive
SCANINIT    d32=a4002008:               ;TAP4: DebugConnect, ForceActive
SCANINIT    d32=a5002008:               ;TAP5: DebugConnect, ForceActive
SCANINIT    d32=a4002108:cl10:          ;enable TAP4,  clock 10 times in RTI
SCANINIT    d32=a5002108:cl10:          ;enable TAP5,  clock 10 times in RTI
SCANINIT    d32=af002108:cl10:          ;enable TAP15, clock 10 times in RTI
SCANINIT    i18=ffffff                  ;scan bypass

; CoreID#0 parameters: MPU_C0 Cortex-A15
#0 CPUTYPE      CORTEX-A15 0xD4140000   ;force APB Debug Base address
#0 DAPPC        0xD4159008              ;Cortex-A15#0 DAP-PC address
#0 STARTUP      HALT
#0 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#0 MEMACCESS    CORE  10                ;memory access via core (8 TCK's access delay)
#0 STEPMODE     OVER                    ;OVER or INTO
#0 BREAKMODE    HARD                    ;SOFT or HARD
#0 SCANPRED     3 14                    ;count for ICEPick TAP and two Cortex-M4
#0 SCANSUCC     0 0                     ;no device after DAP

; CoreID#1 parameters: MPU_C1 Cortex-A15
#1 CPUTYPE      CORTEX-A15 0xD4142000   ;force APB Debug Base address
#1 DAPPC        0xD415900C              ;Cortex-A15#1 DAP-PC address
#1 STARTUP      HALT
#1 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#1 MEMACCESS    CORE  10                ;memory access via core (8 TCK's access delay)
#1 STEPMODE     OVER                    ;OVER or INTO
#1 BREAKMODE    HARD                    ;SOFT or HARD
#1 SCANPRED     3 14                    ;count for ICEPick TAP and two Cortex-M4
#1 SCANSUCC     0 0                     ;no device after DAP

; CoreID#2 parameters: IPU_C0 Cortex-M4
#2 CPUTYPE      CORTEX-M4
#2 STARTUP      WAIT                    ;halt after released from reset
#2 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#2 MEMACCESS    AHB   2                 ;memory access via AHB  (16 TCK's access delay)
#2 STEPMODE     OVER                    ;OVER or INTO
#2 BREAKMODE    HARD                    ;SOFT or HARD
#2 SCANPRED     1 6                     ;count for ICEPick TAP
#2 SCANSUCC     2 8                     ;count for second Cortex-M4 and Cortex-A15 DAP

; CoreID#3 parameters: IPU_C1 Cortex-M4
#3 CPUTYPE      CORTEX-M4
#3 STARTUP      WAIT                    ;halt after released from reset
#3 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#3 MEMACCESS    AHB   2                 ;memory access via AHB  (16 TCK's access delay)
#3 STEPMODE     OVER                    ;OVER or INTO
#3 BREAKMODE    HARD                    ;SOFT or HARD
#3 SCANPRED     2 10                    ;count for ICEPick TAP and first Cortex-M4
#3 SCANSUCC     1 4                     ;count for Cortex-A15 DAP

; CoreID#4 parameters: Dummy core for AHB/AXI accesses
#4 CPUTYPE      CORTEX-A15
#4 STARTUP      IDLE
#4 MEMACCESS    AHB    8
#4 SCANPRED     3 14                    ;count for ICEPick TAP and two Cortex-M4
#4 SCANSUCC     0 0                     ;no device after DAP


[HOST]
#0 PROMPT       MPU_C0#0>
#1 PROMPT       MPU_C1#1>
#2 PROMPT       IPU_C0#0>
#3 PROMPT       IPU_C1#1>
#4 PROMPT       AXI>


[FLASH]


[REGS]
#0 FILE         $regCortex-A15.def
#1 FILE         $regCortex-A15.def
#2 FILE         $regCortex-M4.def
#3 FILE         $regCortex-M4.def