; bdiGDB configuration for Spectrum Digital Netra EVM
; ---------------------------------------------------
;
; There is a Compact TI connetor (J15) on this board.
; To connect to it you need the target cable P/N 90080.
;
; To halt the core as soon as possible after power-up,
; select EMU1=1,EMU0=0 (Wait In Reset mode WIR).
;
;
; Info about the JTAG clock frequency:
; ------------------------------------
; BDI2000:
;   0=Adaptive, 1=16MHz, 2=8MHz, 3=4MHz
;   4=1MHz, 5=500kHz, 6=200kHz, 7=100kHz
;   8=50kHz, 9=20kHz, 10=10kHz
; BDI3000:
;   0=Adaptive, 1=32MHz, 2=16MHz, 3=11MHz,
;   4=8MHz, 5=5MHz, 6=4MHz, 7=1MHz, 8=500kHz
;   9=200kHz, 10=100kHz, 11=50kHz, 12=20kHz,
;   13=10kHz, 14=5kHz, 15=2kHz, 16=1kHz,
;
; Commands supported in the SCANINIT and SCANPOST strings:
; --------------------------------------------------------
;
;  I<n>=<...b2b1b0>   write IR, b0 is first scanned
;  D<n>=<...b2b1b0>   write DR, b0 is first scanned
;                       n  : the number of bits 1..256
;                       bx : a data byte, two hex digits
;  W<n>               wait for n (decimal) micro seconds
;  T1                 assert TRST
;  T0                 release TRST
;  R1                 assert RESET
;  R0                 release RESET
;  CH<n>              clock TCK n (decimal) times with TMS high
;  CL<n>              clock TCK n (decimal) times with TMS low
;
;
[INIT]


[TARGET]
CPUTYPE     CORTEX-A8 0xCB141000        ;force APB Debug Base address
CLOCK       3                           ;BDI3000: 11 MHz JTAG clock
POWERUP     2000                        ;power-up delay
TRST        PUSHPULL                    ;TRST driver type (OPENDRAIN | PUSHPULL)
RESET	    HARD	                ;Reset signal is routed to the debug connector
STARTUP     HALT
ENDIAN      LITTLE                      ;memory model (LITTLE | BIG)
WAKEUP      100
MEMACCESS   CORE  10                    ;memory access via core (80 TCK's access delay)
;MEMACCESS   AHB   8                     ;memory access via AHB  (64 TCK's access delay)

SCANPRED    1 6                         ;count for ICEPick TAP
SCANSUCC    0 0                         ;no device after Cortex-A8

; Configure ICEPick module to make DAP-TAP visible
SCANINIT    t1:w1000:t0:w1000:  ;toggle TRST,
SCANINIT    ch10:w1000:         ;clock TCK with TMS high and wait
SCANINIT    i6=07:d8=89:i6=02:  ;connect and select router
SCANINIT    d32=81000080:       ;IP control: KeepPowered
SCANINIT    d32=ac002008:       ;TAP12: DebugEnable, ForceActive
SCANINIT    d32=e0002008:       ;non-JTAG Core#0: DebugEnable, ForceActive
SCANINIT    d32=ac002108:       ;enable TAP12
SCANINIT    cl10:i10=ffff       ;clock 10 times in RTI, scan bypass


[HOST]
PROMPT      NETRA>


[FLASH]


[REGS]
FILE	$regCortex-A8.def