; ------------------------------------
; bdiGDB configuration LS1021A
; ------------------------------------
;
; This configuration was used to test cross-triggering via CTI.
; Out of reset only core #0 is enabled.
; We use a SCANPOST sequence that write to DCFG_BRR via SAP to enable core#1.
; Once the BDI gets control, it disables MMU, caches and interrupts.
; Then it loads some simple code into internal RAM and let the PC
; of all cores point to this code. The code increments r0 and this is
; used to check if the cores are really halted and restarted synchronously.
;
;

[INIT]
;
#0 WREG control         0x00000000      ;disable MMU and Caches
#1 WREG control         0x00000000      ;disable MMU and Caches
;
#0 WREG cpsr            0x000000d3      ;disable interrupt
#1 WREG cpsr            0x000000d3      ;disable interrupt
;
; Fill some A32 code into SRAM
WM32    0x10000100      0xe1a00000      ;nop
WM32    0x10000104      0xe1a00000      ;nop
WM32    0x10000108      0xe1a00000      ;nop
WM32    0x1000010c      0xe1a00000      ;nop
WM32    0x10000110      0xe1a00000      ;nop
WM32    0x10000114      0xe1a00000      ;nop
WM32    0x10000118      0xe1a00000      ;nop
WM32    0x1000011c      0xe1a00000      ;nop
WM32    0x10000120      0xe1a00000      ;nop
WM32    0x10000124      0xe1a00000      ;nop
WM32    0x10000128      0xe1a00000      ;nop
WM32    0x1000012c      0xe1a00000      ;nop
WM32    0x10000130      0xe1a00000      ;nop
WM32    0x10000134      0xe2800001      ;add	r0, r0, #1
WM32    0x10000138      0xe1a00000      ;nop
WM32    0x1000013c      0xeafffffb      ;b 0x10000130
;
#0 WREG pc              0x10000100      ;set pc to test code
#1 WREG pc              0x10000100      ;set pc to test code
;
#0 WGPR 0               0x00000000      ;clear GPR0
#1 WGPR 0               0x00000000      ;clear GPR0
;


[TARGET]
POWERUP         2000                    ;start delay after power-up detected in ms
CLOCK           16000000                ;JTAG clock 16MHz
TRST            OPENDRAIN               ;TRST driver type (OPENDRAIN | PUSHPULL)
RESET           NONE                    ;see SCANINIT
;
; There is no debug communication possible when RESET is asserted.
; In order be able to hard reset the system we use SCANINIT
SCANINIT        r1:w100:t1:w100:t0:     ;assert reset and toggle TRST
SCANINIT        w100000:r0:w200000:     ;release reset and wait 200 ms
SCANINIT        ch10:w1000              ;clock TCK with TMS high and wait
;
; Release second core by writing to DCFG_BRR via SAP
SCANPOST        i20=021fff:d16=0000:                    ;SAP: high = 0
SCANPOST        i20=024fff:d64=000001EE00E40800:        ;SAP: addr = 0x01EE00E4, write, 32-bit
SCANPOST        i20=025fff:d32=00000003:w1000:          ;SAP: data = 0x00000003
SCANPOST        i20=020fff:w1000:i20=0fffff             ;SAP: reset and bypass
;
;
; CoreID#0 parameters (active core after reset)
#0 CPUTYPE      LS1000  0x80070000      ;force APB Debug Base address
#0 CTI          0x80078000  0x03        ;CTI base address and core group master
#0 STARTUP      HALT                    ;halt as soon as possible
;#0 STARTUP      RUN
;#0 STARTUP      STOP 3000               ;let U-Boot setup the board
#0 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#0 MEMACCESS    CORE    10  0x03        ;memory access via core (80 TCK's access delay)
#0 STEPMODE     OVER                    ;OVER or INTO
#0 BREAKMODE    SOFT                    ;SOFT or HARD
#0 SCANPRED     1 8                     ;count for SAP
#0 SCANSUCC     1 8                     ;count for USBPHY

; CoreID#1 parameters
#1 CPUTYPE      LS1000  0x80072000      ;force APB Debug Base address
#1 CTI          0x80079000  0x02        ;CTI base address and core group slave
#1 STARTUP      HALT                    ;halt as soon as possible
;#1 STARTUP      IDLE                    ;ignore until attached
;#1 STARTUP      WAIT                    ;halt once released to boot
;#1 STARTUP      RUN
#1 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#1 MEMACCESS    CORE    10  0x03        ;memory access via core (80 TCK's access delay)
#1 STEPMODE     OVER                    ;OVER or INTO
#1 BREAKMODE    SOFT                    ;SOFT or HARD
#1 SCANPRED     1 8                     ;count for SAP
#1 SCANSUCC     1 8                     ;count for USBPHY

; CoreID#2 parameters: Dummy core for AHB accesses
#2 CPUTYPE      LS1000
#2 STARTUP      IDLE
#2 MEMACCESS    AHB     8   0x03         ;memory access via AHB (64 TCK's access delay)
#2 SCANPRED     1 8                     ;count for SAP
#2 SCANSUCC     1 8                     ;count for USBPHY
;
; CoreID#3 parameters: Dummy core for SAP accesses
#3 CPUTYPE      LS1000
#3 STARTUP      IDLE
#3 MEMACCESS    SAP                     ;memory access via SAP
#3 SCANPRED     0 0                     ;no TAP before SAP
#3 SCANSUCC     2 12                    ;count for DAP and USBPHY
;


[HOST]
#0 PROMPT       LS1#0>
#1 PROMPT       LS1#1>
#2 PROMPT       AHB>
#3 PROMPT       SAP>

#0 FILE        E:\temp\dump128k.bin
#0 FORMAT      BIN 0x10000000
#1 FILE        E:\temp\dump128k.bin
#1 FORMAT      BIN 0x10000000
#2 FILE        E:\temp\dump128k.bin
#2 FORMAT      BIN 0x10000000
#3 FILE        E:\temp\dump128k.bin
#3 FORMAT      BIN 0x10000000



[FLASH]


[REGS]
FILE            $regLS1021A.def