; ------------------------------------------
; Minimal bdiGDB configuration LS1021A Rev.2
; ------------------------------------------
;

[INIT]
;
; For flash programming with core#0
;#0 WREG control         0x00000000      ;disable MMU and Caches
;#0 WREG cpsr            0x000000d3      ;disable interrupt
;

[TARGET]
POWERUP         2000            ;start delay after power-up detected in ms
CLOCK           16000000        ;JTAG clock 16MHz
TRST            OPENDRAIN       ;TRST driver type (OPENDRAIN | PUSHPULL)
RESET           NONE            ;see SCANINIT
;
; There is no debug communication possible when RESET is asserted.
; In order be able to hard reset the system we use SCANINIT
SCANINIT r1:w100:t1:w100:t0:w100000:      ;assert reset and toggle TRST
;SCANINIT i12=093f:d64=000007ffdfff013d: ;SAP: override RCW source 0_1001_1110
SCANINIT w100000:r0:w500000:              ;release reset and wait 500 ms
SCANINIT ch10:w1000:                      ;clock TCK with TMS high and wait
;
; Release second core by writing to DCFG_BRR via SAP
SCANPOST i12=021f:d16=0000:             ;SAP: high = 0
SCANPOST i12=024f:d64=000001EE00E40800: ;SAP: addr = 0x01EE00E4, write, 32-bit
SCANPOST i12=025f:d32=00000003:w1000:   ;SAP: data = 0x00000003
SCANPOST i12=020f:w1000:i20=0fffff      ;SAP: reset and bypass
;
;
; CoreID#0 parameters (active core after reset)
#0 CPUTYPE      LS1000  0x80070000      ;force APB Debug Base address
#0 STARTUP      HALT                    ;halt as soon as possible
;#0 STARTUP      RUN
;#0 STARTUP      STOP 3000               ;let U-Boot setup the board
#0 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#0 MEMACCESS    CORE    10  0x03        ;memory access via core (80 TCK's access delay)
#0 STEPMODE     OVER                    ;OVER or INTO
#0 BREAKMODE    SOFT                    ;SOFT or HARD
#0 SCANPRED     1 8                     ;count for SAP
#0 SCANSUCC     0 0                     ;no TAP after DAP

; CoreID#1 parameters
#1 CPUTYPE      LS1000  0x80072000      ;force APB Debug Base address
;#1 STARTUP      HALT                    ;halt as soon as possible
;#1 STARTUP      RUN
#1 STARTUP      WAIT                    ;halt once released to boot
;#1 STARTUP      IDLE                    ;ignore until attached
#1 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#1 MEMACCESS    CORE    10  0x03        ;memory access via core (80 TCK's access delay)
#1 STEPMODE     OVER                    ;OVER or INTO
#1 BREAKMODE    SOFT                    ;SOFT or HARD
#1 SCANPRED     1 8                     ;count for SAP
#1 SCANSUCC     0 0                     ;not TAP after DAP

; CoreID#2 parameters: Dummy core for AHB accesses
#2 CPUTYPE      LS1000
#2 STARTUP      IDLE
#2 MEMACCESS    AHB     8   0x03        ;memory access via AHB (64 TCK's access delay)
#2 SCANPRED     1 8                     ;count for SAP
#2 SCANSUCC     0 0                     ;no TAP after DAP
;
; CoreID#3 parameters: Dummy core for SAP accesses
#3 CPUTYPE      LS1000
#3 STARTUP      IDLE
#3 MEMACCESS    SAP                     ;memory access via SAP
#3 ENDIAN       BIG                     ;for NOR flash programming
#3 SCANPRED     0 0                     ;no TAP before SAP
#3 SCANSUCC     1 4                     ;count for DAP
;


[HOST]
#0 PROMPT       LS1#0>
#1 PROMPT       LS1#1>
#2 PROMPT       AHB>
#3 PROMPT       SAP>

#0 FILE         E:\temp\dump128k.bin
#0 FORMAT       BIN 0x10000000
#1 FILE         E:\temp\dump128k.bin
#1 FORMAT       BIN 0x10000000
#2 FILE         E:\temp\dump128k.bin
#2 FORMAT       BIN 0x10000000
#3 FILE         E:\temp\dump128k.bin
#3 FORMAT       BIN 0x10000000


[FLASH]
; JS28F00AM29EWHA (128 Mbyte, MirrorBit)
#0 WORKSPACE    0x10000000      ;workspace in internal OCRAM
#0 CHIPTYPE     MIRRORX16       ;Flash type is JS28F00AM29EWHA
#0 CHIPSIZE     0x08000000      ;visible size of one flash chip in bytes
#0 BUSWIDTH     16 SWAP         ;The width of the flash memory bus in bits
#0 FILE         E:\temp\dump256k.bin
#0 FORMAT       BIN 0x61000000
#0 ERASE        0x61000000 0x20000 4

; JS28F00AM29EWHA (128 Mbyte, MirrorBit)
#1 WORKSPACE    0x10000000      ;workspace in internal OCRAM
#1 CHIPTYPE     MIRRORX16       ;Flash type is JS28F00AM29EWHA
#1 CHIPSIZE     0x08000000      ;visible size of one flash chip in bytes
#1 BUSWIDTH     16 SWAP         ;The width of the flash memory bus in bits
#1 FILE         E:\temp\dump256k.bin
#1 FORMAT       BIN 0x61000000
#1 ERASE        0x61000000 0x20000 4

; JS28F00AM29EWHA (128 Mbyte, MirrorBit)
; use SAP in BE mode for flash programming
#3 CHIPTYPE     MIRRORX16       ;Flash type is JS28F00AM29EWHA
#3 CHIPSIZE     0x08000000      ;visible size of one flash chip in bytes
#3 BUSWIDTH     16              ;The width of the flash memory bus in bits
#3 FILE         E:\temp\dump256k.bin
#3 FORMAT       BIN 0x61000000
#3 ERASE        0x61000000 0x20000 4


[REGS]
#0 FILE         $regLS1021A.def ;also used for core#1 and #2
#3 FILE         $regLS1_SAP.def