; ------------------------------------------------------- ; bdiGDB configuration for iMX6 (SABRE Lite / Nitrogen6X) ; ------------------------------------------------------- ; ; This configuration was used to test cross-triggering via CTI. ; Out of reset only core #0 is accessible. ; The cores #1, #2 and #3 have no clock or are not even powered. ; So there is no debug access to these cores possible until they ; are enabled and clocked. Therefore this configuration let U-Boot ; and Linux run until all 4 cores are enabled. ; This is done with a long POWERUP delay. ; Once the BDI gets control, it disables MMU, caches and interrupts. ; Then it loads some simple code into internal RAM and let the PC ; of all cores point to this code. The code increments r0 and this is ; used to check if the cores are really halted and restarted synchronously. ; ; Here a simple Telnet sequence where a breakpoint on core#0 halts all cores. ; ; IMX6#0>stat ; Core#0: halted 0x00900130 EDBGRQ signal ; Core#1: halted 0x00900130 EDBGRQ signal ; Core#2: halted 0x00900130 Debug Request ; Core#3: halted 0x00900130 EDBGRQ signal ; IMX6#0>cont 0xf ; IMX6#0>stat ; Core#0: running ; Core#1: running ; Core#2: running ; Core#3: running ;IMX6#0>halt 0xf ; - TARGET: core #0 has entered debug mode ; - TARGET: core #1 has entered debug mode ; - TARGET: core #2 has entered debug mode ; - TARGET: core #3 has entered debug mode ; IMX6#0>stat ; Core#0: halted 0x00900130 EDBGRQ signal ; Core#1: halted 0x00900130 EDBGRQ signal ; Core#2: halted 0x00900130 EDBGRQ signal ; Core#3: halted 0x00900130 EDBGRQ signal ; IMX6#0>bi 0x0090013c ; Breakpoint identification is 0 ;IMX6#0>cont 0xf ; - TARGET: core #0 has entered debug mode ; - TARGET: core #1 has entered debug mode ; - TARGET: core #2 has entered debug mode ; - TARGET: core #3 has entered debug mode ; IMX6#0>stat ; Core#0: halted 0x0090013c Breakpoint ; Core#1: halted 0x00900130 EDBGRQ signal ; Core#2: halted 0x00900130 EDBGRQ signal ; Core#3: halted 0x00900130 EDBGRQ signal ; IMX6#0>; ; ; ; [INIT] #0 WREG control 0x00000000 ;disable MMU and Caches #1 WREG control 0x00000000 ;disable MMU and Caches #2 WREG control 0x00000000 ;disable MMU and Caches #3 WREG control 0x00000000 ;disable MMU and Caches ; #0 WREG cpsr 0x000000d3 ;disable interrupt #1 WREG cpsr 0x000000d3 ;disable interrupt #2 WREG cpsr 0x000000d3 ;disable interrupt #3 WREG cpsr 0x000000d3 ;disable interrupt ; ; Fill some A32 code into SRAM WM32 0x00900100 0xe1a00000 ;nop WM32 0x00900104 0xe1a00000 ;nop WM32 0x00900108 0xe1a00000 ;nop WM32 0x0090010c 0xe1a00000 ;nop WM32 0x00900110 0xe1a00000 ;nop WM32 0x00900114 0xe1a00000 ;nop WM32 0x00900118 0xe1a00000 ;nop WM32 0x0090011c 0xe1a00000 ;nop WM32 0x00900120 0xe1a00000 ;nop WM32 0x00900124 0xe1a00000 ;nop WM32 0x00900128 0xe1a00000 ;nop WM32 0x0090012c 0xe1a00000 ;nop WM32 0x00900130 0xe1a00000 ;nop WM32 0x00900134 0xe2800001 ;add r0, r0, #1 WM32 0x00900138 0xe1a00000 ;nop WM32 0x0090013c 0xeafffffb ;b 0x80000130 ; #0 WREG pc 0x00900100 ;set pc to test code #1 WREG pc 0x00900100 ;set pc to test code #2 WREG pc 0x00900100 ;set pc to test code #3 WREG pc 0x00900100 ;set pc to test code ; #0 WGPR 0 0x00000000 ;clear GPR0 #1 WGPR 0 0x00000000 ;clear GPR0 #2 WGPR 0 0x00000000 ;clear GPR0 #3 WGPR 0 0x00000000 ;clear GPR0 ; [TARGET] POWERUP 8000 ;start delay after power-up detected in ms CLOCK 8000000 ;JTAG clock 8MHz TRST OPENDRAIN ;TRST driver type (OPENDRAIN | PUSHPULL) RESET NONE ;see SCANINIT ; CoreID#0 parameters (active core after reset) #0 CPUTYPE CORTEX-A9 0x82150000 ;force APB Debug Base address #0 CTI 0x82158000 0x0f ;CTI base address and core group master #0 STARTUP HALT #0 ENDIAN LITTLE ;memory model (LITTLE | BIG) #0 MEMACCESS CORE 10 ;memory access via core (80 TCK's access delay) #0 STEPMODE OVER ;OVER or INTO #0 BREAKMODE SOFT ;SOFT or HARD #0 SCANPRED 2 9 ;count for SJC and SDMA #0 SCANSUCC 0 0 ;no device after DAP ; CoreID#1 parameters #1 CPUTYPE CORTEX-A9 0x82152000 ;force APB Debug Base address #1 CTI 0x82159000 0x02 ;CTI base address and core group slave #1 STARTUP HALT #1 ENDIAN LITTLE ;memory model (LITTLE | BIG) #1 MEMACCESS CORE 10 ;memory access via core (80 TCK's access delay) #1 STEPMODE OVER ;OVER or INTO #1 BREAKMODE SOFT ;SOFT or HARD #1 SCANPRED 2 9 ;count for SJC and SDMA #1 SCANSUCC 0 0 ;no device after DAP ; CoreID#2 parameters #2 CPUTYPE CORTEX-A9 0x82154000 ;force APB Debug Base address #2 CTI 0x8215A000 0x04 ;CTI base address and core group slave #2 STARTUP HALT #2 ENDIAN LITTLE ;memory model (LITTLE | BIG) #2 MEMACCESS CORE 10 ;memory access via core (80 TCK's access delay) #2 STEPMODE OVER ;OVER or INTO #2 BREAKMODE SOFT ;SOFT or HARD #2 SCANPRED 2 9 ;count for SJC and SDMA #2 SCANSUCC 0 0 ;no device after DAP ; CoreID#3 parameters #3 CPUTYPE CORTEX-A9 0x82156000 ;force APB Debug Base address #3 CTI 0x8215B000 0x08 ;CTI base address and core group slave #3 STARTUP HALT #3 ENDIAN LITTLE ;memory model (LITTLE | BIG) #3 MEMACCESS CORE 10 ;memory access via core (80 TCK's access delay) #3 STEPMODE OVER ;OVER or INTO #3 BREAKMODE SOFT ;SOFT or HARD #3 SCANPRED 2 9 ;count for SJC and SDMA #3 SCANSUCC 0 0 ;no device after DAP [HOST] #0 PROMPT IMX6#0> #1 PROMPT IMX6#1> #2 PROMPT IMX6#2> #3 PROMPT IMX6#3> [FLASH] [REGS] FILE $regIMX6CTI.def