; ---------------------------------------------------------------
; Minimal bdiGDB configuration for iMX6 (SABRE Lite / Nitrogen6X)
; ---------------------------------------------------------------
;
; Out of reset only core #0 is accessible.
; The cores #1, #2 and #3 have no clock or are not even powered.
; So there is no debug access to these cores possible until they
; are enabled and clocked. Therefore startup mode IDLE is used.
; You can attach these cores via Telnet once they are alive.
;
;
; Commands supported in the SCANINIT and SCANPOST strings:
;
;  I<n>=<...b2b1b0>   write IR, b0 is first scanned
;  D<n>=<...b2b1b0>   write DR, b0 is first scanned
;                       n  : the number of bits 1..256
;                       bx : a data byte, two hex digits
;  W<n>               wait for n (decimal) micro seconds
;  T1                 assert TRST
;  T0                 release TRST
;  R1                 assert RESET
;  R0                 release RESET
;  CH<n>              clock TCK n (decimal) times with TMS high
;  CL<n>              clock TCK n (decimal) times with TMS low
;
;
; Challenge/Response:
;
; SCANINIT  i13=ffff                ;bypass all TAP's
; SCANINIT  i13=0cff                ;Security Output challenge
; SCANINIT  d64=0000000000000000    ;hidden read challenge
; SCANINIT  i13=0dff                ;Security Enter response
; SCANINIT  d64=0123456789abcdef    ;scan in correct response
;

[INIT]


[TARGET]
POWERUP         2000                    ;start delay after power-up detected in ms
CLOCK           8000000                 ;JTAG clock 8MHz
TRST            OPENDRAIN               ;TRST driver type (OPENDRAIN | PUSHPULL)
RESET           NONE                    ;see SCANINIT
;
; There is no debug communication possible when RESET is asserted.
; In order be able to hard reset the system we use SCANINIT
SCANINIT        r1:w100:t1:w100:t0:     ;assert reset and toggle TRST
SCANINIT        r0:w1000000:            ;release reset and wait 1 sec (consider reset delay in TPS3808)
SCANINIT        ch10:w1000              ;clock TCK with TMS high and wait
;
;
; CoreID#0 parameters (active core after reset)
#0 CPUTYPE      CORTEX-A9 0x82150000    ;force APB Debug Base address
#0 STARTUP      HALT                    ;halt as soon as possible
;#0 STARTUP      STOP 3000               ;let U-Boot setup the board
#0 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#0 MEMACCESS    CORE  10                ;memory access via core (80 TCK's access delay)
#0 STEPMODE     OVER                    ;OVER or INTO
#0 BREAKMODE    HARD                    ;SOFT or HARD
#0 SCANPRED     2 9                     ;count for SJC and SDMA
#0 SCANSUCC     0 0                     ;no device after DAP

; CoreID#1 parameters
#1 CPUTYPE      CORTEX-A9 0x82152000    ;force APB Debug Base address
#1 STARTUP      IDLE                    ;ignore until attached
#1 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#1 MEMACCESS    CORE  10                ;memory access via core (80 TCK's access delay)
#1 STEPMODE     OVER                    ;OVER or INTO
#1 BREAKMODE    HARD                    ;SOFT or HARD
#1 SCANPRED     2 9                     ;count for SJC and SDMA
#1 SCANSUCC     0 0                     ;no device after DAP

; CoreID#2 parameters
#2 CPUTYPE      CORTEX-A9 0x82154000    ;force APB Debug Base address
#2 STARTUP      IDLE                    ;ignore until attached
#2 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#2 MEMACCESS    CORE  10                ;memory access via core (80 TCK's access delay)
#2 STEPMODE     OVER                    ;OVER or INTO
#2 BREAKMODE    HARD                    ;SOFT or HARD
#2 SCANPRED     2 9                     ;count for SJC and SDMA
#2 SCANSUCC     0 0                     ;no device after DAP

; CoreID#3 parameters
#3 CPUTYPE      CORTEX-A9 0x82156000    ;force APB Debug Base address
#3 STARTUP      IDLE                    ;ignore until attached
#3 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#3 MEMACCESS    CORE  10                ;memory access via core (80 TCK's access delay)
#3 STEPMODE     OVER                    ;OVER or INTO
#3 BREAKMODE    HARD                    ;SOFT or HARD
#3 SCANPRED     2 9                     ;count for SJC and SDMA
#3 SCANSUCC     0 0                     ;no device after DAP



[HOST]
#0 PROMPT       IMX6#0>
#1 PROMPT       IMX6#1>
#2 PROMPT       IMX6#2>
#3 PROMPT       IMX6#3>


[FLASH]


[REGS]
FILE            $regCortex-A9.def