; --------------------------------------
; Minimal bdiGDB configuration for iMX51
; --------------------------------------
;
; Info about the JTAG clock frequency:
; ------------------------------------
; BDI2000:
;   0=Adaptive, 1=16MHz, 2=8MHz, 3=4MHz
;   4=1MHz, 5=500kHz, 6=200kHz, 7=100kHz
;   8=50kHz, 9=20kHz, 10=10kHz
; BDI3000:
;   0=Adaptive, 1=32MHz, 2=16MHz, 3=11MHz,
;   4=8MHz, 5=5MHz, 6=4MHz, 7=1MHz, 8=500kHz
;   9=200kHz, 10=100kHz, 11=50kHz, 12=20kHz,
;   13=10kHz, 14=5kHz, 15=2kHz, 16=1kHz,
;
; Commands supported in the SCANINIT and SCANPOST strings:
;
;  I<n>=<...b2b1b0>   write IR, b0 is first scanned
;  D<n>=<...b2b1b0>   write DR, b0 is first scanned
;                       n  : the number of bits 1..256
;                       bx : a data byte, two hex digits
;  W<n>               wait for n (decimal) micro seconds
;  T1                 assert TRST
;  T0                 release TRST
;  R1                 assert RESET
;  R0                 release RESET
;  CH<n>              clock TCK n (decimal) times with TMS high
;  CL<n>              clock TCK n (decimal) times with TMS low
;
;

[INIT]


[TARGET]
POWERUP         2000                    ;start delay after power-up detected in ms
CLOCK           2                       ;BDI2000: JTAG clock 8MHz
;CLOCK           4                       ;BDI3000: JTAG clock 8MHz
TRST            OPENDRAIN               ;TRST driver type (OPENDRAIN | PUSHPULL)
RESET           NONE                    ;see SCANINIT
;
CPUTYPE         CORTEX-A8 0xe0008000    ;Cortex-A8, APB core debug base at 0xe0008000
STARTUP         HALT                    ;halt as soon as possible
ENDIAN          LITTLE                  ;memory model (LITTLE | BIG)
BREAKMODE       HARD                    ;SOFT or HARD
MEMACCESS       CORE   10               ;memory access via Core  (80 TCK's access delay)
;MEMACCESS       AHB    8                ;memory access via AHB  (64 TCK's access delay)
;
SCANPRED        2 9                     ;two devices before DAP
SCANSUCC        0 0                     ;no devices after DAP
;
; There is no debug communication possible when RESET is asserted.
; In order be able to hard reset the system we use SCANINIT
SCANINIT        r1:w100:t1:w100:t0:     ;assert reset and toggle TRST
SCANINIT        w1000:ch10:w1000:       ;clock TCK with TMS high and wait
SCANINIT        r0:w10000               ;release reset
;


[HOST]
IP              151.120.25.119
PROMPT          iMX51>


[FLASH]


[REGS]
FILE            $regIMX51.def