; ----------------------------------------------------
; bdiGDB configuration for Cortex-A15 (ARNDALE5 Board)
; ----------------------------------------------------
;
; This configuration was used to test cross-triggering via CTI.
; This configuration let U-Boot run until both cores are enabled.
; This is done with a long POWERUP delay.
; Once the BDI gets control, it disables MMU, caches and interrupts.
; Then it loads some simple code into DRAM and lets the PC
; of all cores point to this code. The code increments r0 and this is
; used to check if the cores are really halted and restarted synchronously.


[INIT]
#0 WREG sctlr           0x00000000      ;disable MMU and Caches
#1 WREG sctlr           0x00000000      ;disable MMU and Caches
;
#0 WREG cpsr            0x000001d3      ;disable interrupt
#1 WREG cpsr            0x000001d3      ;disable interrupt
;
; Fill some A32 code into SRAM
WM32    0x43000100      0xe1a00000      ;nop
WM32    0x43000104      0xe1a00000      ;nop
WM32    0x43000108      0xe1a00000      ;nop
WM32    0x4300010c      0xe1a00000      ;nop
WM32    0x43000110      0xe1a00000      ;nop
WM32    0x43000114      0xe1a00000      ;nop
WM32    0x43000118      0xe1a00000      ;nop
WM32    0x4300011c      0xe1a00000      ;nop
WM32    0x43000120      0xe1a00000      ;nop
WM32    0x43000124      0xe1a00000      ;nop
WM32    0x43000128      0xe1a00000      ;nop
WM32    0x4300012c      0xe1a00000      ;nop
WM32    0x43000130      0xe1a00000      ;nop
WM32    0x43000134      0xe2800001      ;add	r0, r0, #1
WM32    0x43000138      0xe1a00000      ;nop
WM32    0x4300013c      0xeafffffb      ;b 0x43000130
;
#0 WREG pc              0x43000100      ;set pc to test code
#1 WREG pc              0x43000100      ;set pc to test code
;
#0 WGPR 0               0x00000000      ;clear GPR0
#1 WGPR 0               0x00000000      ;clear GPR0
;


[TARGET]
POWERUP         4000            ;start delay after power-up detected in ms
CLOCK           8000000         ;JTAG clock 8 MHz
TRST            PUSHPULL        ;TRST driver type (OPENDRAIN | PUSHPULL)
RESET	        NONE            ;RESET seems not to be routed
WAKEUP	        100             ;wait after reset released
;
; CoreID#0 parameters (active core after reset)
#0 CPUTYPE      CORTEX-A15 0x80010000   ;force APB Debug Base address
#0 CTI          0x80018000 0x03         ;CTI base address and core group master
#0 STARTUP      HALT                    ;halt immediately after reset
#0 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
#0 BREAKMODE    HARD                    ;SOFT or HARD
#0 MEMACCESS    CORE   10               ;memory access via Core  (80 TCK's access delay)
;
; CoreID#1 parameters: Second Cortex-A15 core
#1 CPUTYPE      CORTEX-A15 0x80012000   ;force APB Debug Base address
#1 CTI          0x80019000 0x02         ;CTI base address and core group slave
#1 STARTUP      HALT
#1 ENDIAN       LITTLE
#1 BREAKMODE    HARD
#1 MEMACCESS    CORE   10
;
; CoreID#2 parameters: Dummy core for AXI accesses
#2 CPUTYPE      CORTEX-A15
#2 STARTUP      IDLE
#2 MEMACCESS    AXI    8
;


[HOST]
#0 PROMPT          A15#0>
#1 PROMPT          A15#1>
#2 PROMPT          AXI>


[FLASH]


[REGS]
FILE            $regCortex-A15.def