; ------------------------------------------------------------
; Minimal bdiGDB configuration for Cortex-A15 (ARNDALE5 Board)
; ------------------------------------------------------------
;
; Commands supported in the SCANINIT and SCANPOST strings:
;
;  I<n>=<...b2b1b0>   write IR, b0 is first scanned
;  D<n>=<...b2b1b0>   write DR, b0 is first scanned
;                       n  : the number of bits 1..256
;                       bx : a data byte, two hex digits
;  W<n>               wait for n (decimal) micro seconds
;  T1                 assert TRST
;  T0                 release TRST
;  R1                 assert RESET
;  R0                 release RESET
;  CH<n>              clock TCK n (decimal) times with TMS high
;  CL<n>              clock TCK n (decimal) times with TMS low
;
;
; Low level access to CoreSight debug system:
; -------------------------------------------
; RDP   <addr>                 display Debug Port (DP) register
; RAP   <addr>                 display Access Port (AP) register
; RDBG  <nbr>  [<cnt>]         display core debug register
; WDP   <addr> <value>         modify Debug Port (DP) register
; WAP   <addr> <value>         modify Access Port (AP) register
; WDBG  <nbr>  <value>         modify core debug register
; MDAPB <addr> [<cnt>]         display APB memory
; MMAPB <addr> <value>         modify  APB memory
; MDAHB <addr> [<cnt>]         display AHB/AXI memory (32-bit)
; MMAHB <addr> <value>         modify  AHB/AXI memory (32-bit)
;


[INIT]
;WREG    par_64  0x1234567890abcdef

[TARGET]
POWERUP         2000            ;start delay after power-up detected in ms
CLOCK           8000000         ;JTAG clock 8 MHz
TRST            PUSHPULL        ;TRST driver type (OPENDRAIN | PUSHPULL)
RESET	        NONE            ;RESET seems not to be routed
WAKEUP	        100             ;wait after reset released
;
; CoreID#0 parameters (active core after reset)
#0 CPUTYPE      CORTEX-A15 0    ;Core is Cortex-A15
;#0 STARTUP      HALT            ;halt immediately after reset
#0 STARTUP      STOP 2000       ;let U-boot run for 2 seconds
;#0 STARTUP      RUN             ;let U-boot run
;#0 STARTUP      IDLE            ;don't access until attached
#0 ENDIAN       LITTLE          ;memory model (LITTLE | BIG)
#0 BREAKMODE    HARD            ;SOFT or HARD
#0 MEMACCESS    CORE   10       ;memory access via Core  (80 TCK's access delay)
;
; CoreID#1 parameters: Second Cortex-A15 core
#1 CPUTYPE      CORTEX-A15 1
#1 STARTUP      IDLE
#1 ENDIAN       LITTLE
#1 BREAKMODE    SOFT
#1 MEMACCESS    CORE   10
;
; CoreID#2 parameters: Dummy core for AXI accesses
#2 CPUTYPE      CORTEX-A15
#2 STARTUP      IDLE
#2 MEMACCESS    AXI    8
;


[HOST]
#0 PROMPT          A15#0>
#1 PROMPT          A15#1>
#2 PROMPT          AXI>


[FLASH]


[REGS]
FILE            $regCortex-A15.def