; ----------------------------------------------
; Minimal bdiGDB configuration for Cavium CN88XX
; ----------------------------------------------
;
; Commands supported in the SCANINIT and SCANPOST strings:
;
;  I<n>=<...b2b1b0>   write IR, b0 is first scanned
;  D<n>=<...b2b1b0>   write DR, b0 is first scanned
;                       n  : the number of bits 1..256
;                       bx : a data byte, two hex digits
;  W<n>               wait for n (decimal) micro seconds
;  T1                 assert TRST
;  T0                 release TRST
;  R1                 assert RESET
;  R0                 release RESET
;  CH<n>              clock TCK n (decimal) times with TMS high
;  CL<n>              clock TCK n (decimal) times with TMS low
;  M<addr>=<value>    write 32-bit to AHB/AXI
;  A<addr>=<value>    write 32-bit to APB
;  P<addr>=<value>    write 32-bit to Access Port register
;
;
; Low level access to CoreSight debug system:
; -------------------------------------------
; RDP   <addr>                 display Debug Port (DP) register
; RAP   <addr>                 display Access Port (AP) register
; RDBG  <nbr>  [<cnt>]         display core debug register
; WDP   <addr> <value>         modify Debug Port (DP) register
; WAP   <addr> <value>         modify Access Port (AP) register
; WDBG  <nbr>  <value>         modify core debug register
; MDAPB <addr> [<cnt>]         display APB memory
; MMAPB <addr> <value>         modify  APB memory
; MDAHB <addr> [<cnt>]         display AHB memory (32-bit)
; MMAHB <addr> <value>         modify  AHB memory (32-bit)
; MDAXI <addr> [<cnt>]         display AXI memory (64-bit)
; MMAXI <addr> <value>         modify  AXI memory (64-bit)
;


[INIT]
;
#0 WREG mdscr_el1       0x00008000              ;Enable Hardware Breakpoints via MDSCR-MDE
;

[TARGET]
POWERUP         3000                    ;start delay after power-up detected in ms
CLOCK           8000000                 ;JTAG clock 8 MHz
TRST            PUSHPULL                ;TRST driver type (OPENDRAIN | PUSHPULL)
WAKEUP          100                     ;wait after reset released
;
; We use SCANINIT to execute a hard and a debug soft reset via DP.CSW
SCANINIT        r1:w1000:t1:w1000:t0:   ;assert reset and toggle TRST
SCANINIT        w1000:r0:w100000:       ;release hard reset and wait
SCANINIT        w100000:ch10:w1000:     ;wait and clock TCK with TMS high
SCANINIT        i4=0a:d35=0020000002    ;set DP.CSW[26] = 1
SCANINIT        w100000:                ;wait some time
SCANINIT        i4=0a:d35=0000000002    ;set DP.CSW[26] = 0
SCANINIT        w100000:                ;wait some time
;
; CoreID#0 parameters (active core after reset)
#0 CPUTYPE      THUNDERX  0x88000000    ;THUNDERX core 0
#0 RESET        SOFT                    ;request a warm reset via EDPRCR
;#0 STARTUP      IDLE                    ;don't access until attached
;#0 STARTUP      HALT                    ;halt as soon as possible
#0 STARTUP      STOP 3000               ;let boot code setup the system
#0 ENDIAN       LITTLE                  ;memory model (LITTLE | BIG)
;#0 VECTOR       CATCH  RST OSU TDA      ;Reset and OS unlock catch, Trap SW access
#0 VECTOR       CATCH  OSU TDA          ;OS unlock catch, Trap SW access
#0 BREAKMODE    HARD                    ;SOFT or HARD
#0 MEMACCESS    CORE   10               ;memory access via Core  (80 TCK's access delay)
;
; CoreID#4 parameters: Dummy core for CVM-AP accesses
#1 CPUTYPE      THUNDERX
#1 STARTUP      IDLE
#1 MEMACCESS    AXI    8  0x00
;


[HOST]
#0 PROMPT       THX#0>
#1 PROMPT       CVM>


[FLASH]


[REGS]
#0 FILE         $regCN88XX-EL3.def
#1 FILE         $regCN88XX-CSR.def