; ------------------------------------------------------------------- ; bdiGDB configuration for ARMV8 CTI Tests (AMP Mustang X-Gene board) ; ------------------------------------------------------------------- ; ; This configuration was used to test cross-triggering via CTI. ; Out of reset only core #0 is accessible. ; So the BDI let the system run until U-boot has enabled all cores. ; This is done with a long delay in the SCANINIT sequence. ; Once the BDI gets control the caches are disabled. ; Then it loads some simple code into internal RAM and let the PC ; of all cores point to this code. The code increments r5 and this is ; used to check if the cores are really halted and restarted synchronously. ; This configuration also defines the core group options used when GDB ; sends the "continue" command. ; ; Here a simple Telnet sequence where a breakpoint on core#0 halts all cores. ; ; XGENE#0>stat ; Core#0: halted 0x000000001d000028 External Debug Request ; Core#1: halted 0x000000001d000028 External Debug Request ; Core#2: halted 0x000000001d000028 External Debug Request ; Core#3: halted 0x000000001d000028 External Debug Request ; Core#4: halted 0x000000001d000028 External Debug Request ; Core#5: halted 0x000000001d000028 External Debug Request ; Core#6: halted 0x000000001d000028 External Debug Request ; Core#7: halted 0x000000001d000028 External Debug Request ; Core#8: detached ; ; XGENE#0>cont 0xff ; XGENE#0>stat ; Core#0: running ; Core#1: running ; Core#2: running ; Core#3: running ; Core#4: running ; Core#5: running ; Core#6: running ; Core#7: running ; Core#8: detached ; ; XGENE#0>halt ; Core number : 0 ; Core state : debug (AArch64 EL2) ; Debug entry cause : External Debug Request ; Current PC : 0x000000001d000028 ; Current CPSR : 0x800003c9 (EL2h) ; - TARGET: core #1 has entered debug mode ; - TARGET: core #2 has entered debug mode ; - TARGET: core #3 has entered debug mode ; - TARGET: core #4 has entered debug mode ; - TARGET: core #5 has entered debug mode ; - TARGET: core #6 has entered debug mode ; - TARGET: core #7 has entered debug mode ; ; XGENE#0>stat ; Core#0: halted 0x000000001d000028 External Debug Request ; Core#1: halted 0x000000001d000028 External Debug Request ; Core#2: halted 0x000000001d000028 External Debug Request ; Core#3: halted 0x000000001d000028 External Debug Request ; Core#4: halted 0x000000001d000028 External Debug Request ; Core#5: halted 0x000000001d000028 External Debug Request ; Core#6: halted 0x000000001d000028 External Debug Request ; Core#7: halted 0x000000001d000028 External Debug Request ; Core#8: detached ; ; XGENE#0>bi 0x1d000038 ; Breakpoint identification is 0 ; ; XGENE#0>cont 0xff ; - TARGET: core #0 has entered debug mode ; - TARGET: core #1 has entered debug mode ; - TARGET: core #2 has entered debug mode ; - TARGET: core #3 has entered debug mode ; - TARGET: core #4 has entered debug mode ; - TARGET: core #5 has entered debug mode ; - TARGET: core #6 has entered debug mode ; - TARGET: core #7 has entered debug mode ; ; XGENE#0>stat ; Core#0: halted 0x000000001d000038 Breakpoint ; Core#1: halted 0x000000001d000028 External Debug Request ; Core#2: halted 0x000000001d000028 External Debug Request ; Core#3: halted 0x000000001d000028 External Debug Request ; Core#4: halted 0x000000001d000028 External Debug Request ; Core#5: halted 0x000000001d000028 External Debug Request ; Core#6: halted 0x000000001d000028 External Debug Request ; Core#7: halted 0x000000001d000028 External Debug Request ; Core#8: detached ; ; [INIT] ; ; Fill some A64 code into SRAM WM32 0x1d000000 0xd503201f ;nop WM32 0x1d000004 0xd503201f ;nop WM32 0x1d000008 0xd503201f ;nop WM32 0x1d00000c 0xd503201f ;nop WM32 0x1d000010 0xd503201f ;nop WM32 0x1d000014 0xd503201f ;nop WM32 0x1d000018 0xd503201f ;nop WM32 0x1d00001c 0xd503201f ;nop WM32 0x1d000020 0xd503201f ;nop WM32 0x1d000024 0xd503201f ;nop WM32 0x1d000028 0xd503201f ;nop WM32 0x1d00002c 0xd503201f ;nop WM32 0x1d000030 0x910004a5 ;add x5, x5, #0x1 WM32 0x1d000034 0xd503201f ;nop WM32 0x1d000038 0xd503201f ;nop WM32 0x1d00003c 0x17fffffb ;b 0x1d000028 ; ; Fill some A32 code into SRAM WM32 0x1d000100 0xe1a00000 ;nop WM32 0x1d000104 0xe1a00000 ;nop WM32 0x1d000108 0xe1a00000 ;nop WM32 0x1d00010c 0xe1a00000 ;nop WM32 0x1d000110 0xe1a00000 ;nop WM32 0x1d000114 0xe1a00000 ;nop WM32 0x1d000118 0xe1a00000 ;nop WM32 0x1d00011c 0xe1a00000 ;nop WM32 0x1d000120 0xe1a00000 ;nop WM32 0x1d000124 0xe1a00000 ;nop WM32 0x1d000128 0xe1a00000 ;nop WM32 0x1d00012c 0xe1a00000 ;nop WM32 0x1d000130 0xe1a00000 ;nop WM32 0x1d000134 0xe1a00000 ;nop WM32 0x1d000138 0xe1a00000 ;nop WM32 0x1d00013c 0xeafffffb ;b 0x1d000130 ; ; Fill some Thumb code into SRAM WM16 0x1d000200 0x46c0 ;nop WM16 0x1d000202 0x46c0 ;nop WM16 0x1d000204 0x46c0 ;nop WM16 0x1d000206 0x46c0 ;nop WM16 0x1d000208 0x46c0 ;nop WM16 0x1d00020a 0x46c0 ;nop WM16 0x1d00020c 0x46c0 ;nop WM16 0x1d00020e 0x46c0 ;nop WM16 0x1d000210 0x46c0 ;nop WM16 0x1d000212 0x46c0 ;nop WM16 0x1d000214 0x46c0 ;nop WM16 0x1d000216 0x46c0 ;nop WM16 0x1d000218 0x46c0 ;nop WM16 0x1d00021a 0x46c0 ;nop WM16 0x1d00021c 0x46c0 ;nop WM16 0x1d00021e 0xe7f8 ;b 0x1d000212 ; #0 WREG pc 0x1d000000 ;set PC to test code #1 WREG pc 0x1d000000 ;set PC to test code #2 WREG pc 0x1d000000 ;set PC to test code #3 WREG pc 0x1d000000 ;set PC to test code #4 WREG pc 0x1d000000 ;set PC to test code #5 WREG pc 0x1d000000 ;set PC to test code #6 WREG pc 0x1d000000 ;set PC to test code #7 WREG pc 0x1d000000 ;set PC to test code ; #0 WGPR 5 0 ;clear register x5 #1 WGPR 5 0 ;clear register x5 #2 WGPR 5 0 ;clear register x5 #3 WGPR 5 0 ;clear register x5 #4 WGPR 5 0 ;clear register x5 #5 WGPR 5 0 ;clear register x5 #6 WGPR 5 0 ;clear register x5 #7 WGPR 5 0 ;clear register x5 ; #0 WREG sctlr_el2 0x30c50830 ;disable cache/MMU #1 WREG sctlr_el2 0x30c50830 ;disable cache/MMU #2 WREG sctlr_el2 0x30c50830 ;disable cache/MMU #3 WREG sctlr_el2 0x30c50830 ;disable cache/MMU #4 WREG sctlr_el2 0x30c50830 ;disable cache/MMU #5 WREG sctlr_el2 0x30c50830 ;disable cache/MMU #6 WREG sctlr_el2 0x30c50830 ;disable cache/MMU #7 WREG sctlr_el2 0x30c50830 ;disable cache/MMU ; [TARGET] POWERUP 5000 ;start delay after power-up detected in ms CLOCK 8000000 ;JTAG clock 8 MHz TRST OPENDRAIN ;TRST driver type (OPENDRAIN | PUSHPULL) RESET NONE ;see SCANINIT ; ; There is no debug communication possible when RESET is asserted. ; In order be able to hard reset the system we use SCANINIT ; and we route a wire from BDI TargetB-13 to J3-2 SCANINIT r1:w1000:t1:w1000:t0: ;assert reset and toggle TRST SCANINIT w10000:r0:w10000000 ;release reset and wait until U-boot releases all cores ; ; ; CoreID#0 parameters (active core after reset) #0 CPUTYPE X-GENE 0xfc010000 ;X-Gene CPU 0 #0 CTI 0xfc020000 0xff ;CTI base address and core group master #0 STARTUP HALT ;halt as soon as possible #0 ENDIAN LITTLE ;memory model (LITTLE | BIG) #0 VECTOR CATCH RST OSU TDA ;Reset and OS unlock catch, Trap SW access #0 BREAKMODE SOFT ;SOFT or HARD #0 MEMACCESS CORE 10 ;memory access via Core (80 TCK's access delay) ; ; CoreID#1 parameters: #1 CPUTYPE X-GENE 0xfc110000 ;X-Gene CPU 1 #1 CTI 0xfc120000 0x02 ;CTI base address and core group slave #1 STARTUP HALT #1 ENDIAN LITTLE #1 BREAKMODE HARD #1 MEMACCESS CORE 10 ; ; CoreID#2 parameters: #2 CPUTYPE X-GENE 0xfc210000 ;X-Gene CPU 2 #2 CTI 0xfc220000 0x04 ;CTI base address and core group slave #2 STARTUP HALT #2 ENDIAN LITTLE #2 BREAKMODE HARD #2 MEMACCESS CORE 10 ; ; CoreID#3 parameters: #3 CPUTYPE X-GENE 0xfc310000 ;X-Gene CPU 3 #3 CTI 0xfc320000 0x08 ;CTI base address and core group slave #3 STARTUP HALT #3 ENDIAN LITTLE #3 BREAKMODE HARD #3 MEMACCESS CORE 10 ; ; CoreID#4 parameters: #4 CPUTYPE X-GENE 0xfc410000 ;X-Gene CPU 4 #4 CTI 0xfc420000 0x10 ;CTI base address and core group slave #4 STARTUP HALT #4 ENDIAN LITTLE #4 BREAKMODE HARD #4 MEMACCESS CORE 10 ; ; CoreID#5 parameters: #5 CPUTYPE X-GENE 0xfc510000 ;X-Gene CPU 5 #5 CTI 0xfc520000 0x20 ;CTI base address and core group slave #5 STARTUP HALT #5 ENDIAN LITTLE #5 BREAKMODE HARD #5 MEMACCESS CORE 10 ; ; CoreID#6 parameters: #6 CPUTYPE X-GENE 0xfc610000 ;X-Gene CPU 6 #6 CTI 0xfc620000 0x40 ;CTI base address and core group slave #6 STARTUP HALT #6 ENDIAN LITTLE #6 BREAKMODE HARD #6 MEMACCESS CORE 10 ; ; CoreID#7 parameters: #7 CPUTYPE X-GENE 0xfc710000 ;X-Gene CPU 7 #7 CTI 0xfc720000 0x80 ;CTI base address and core group slave #7 STARTUP HALT #7 ENDIAN LITTLE #7 BREAKMODE HARD #7 MEMACCESS CORE 10 ; ; CoreID#8 parameters: Dummy core for AXI accesses #8 CPUTYPE X-GENE #8 STARTUP IDLE #8 MEMACCESS AXI 8 ;memory access via AXI (64 TCK's access delay) ; [HOST] FILE E:\temp\dump256k.bin FORMAT BIN 0x1d001000 ; #0 PROMPT XGENE#0> #1 PROMPT XGENE#1> #2 PROMPT XGENE#2> #3 PROMPT XGENE#3> #4 PROMPT XGENE#4> #5 PROMPT XGENE#5> #6 PROMPT XGENE#6> #7 PROMPT XGENE#7> #8 PROMPT AXI> ;Assign GDB sessions ;------------------- #0 DEBUGPORT 2800 #1 DEBUGPORT 2801 #2 DEBUGPORT 2802 #3 DEBUGPORT 2803 #4 DEBUGPORT 2804 #5 DEBUGPORT 2805 #6 DEBUGPORT 2806 #7 DEBUGPORT 2807 [FLASH] ; only to test helper code execution WORKSPACE 0x1D000000 CHIPTYPE AM29BX16 CHIPSIZE 0x40000 BUSWIDTH 16 FILE E:/temp/dump16k.bin FORMAT BIN 0x1d010000 [REGS] ;FILE $regARMV8.def FILE $regARMV8-EL2.def