; -------------------------------------- ; Minimal bdiGDB configuration for ARMV8 ; -------------------------------------- ; ; Commands supported in the SCANINIT and SCANPOST strings: ; ; I=<...b2b1b0> write IR, b0 is first scanned ; D=<...b2b1b0> write DR, b0 is first scanned ; n : the number of bits 1..256 ; bx : a data byte, two hex digits ; W wait for n (decimal) micro seconds ; T1 assert TRST ; T0 release TRST ; R1 assert RESET ; R0 release RESET ; CH clock TCK n (decimal) times with TMS high ; CL clock TCK n (decimal) times with TMS low ; M= write 32-bit to AHB/AXI ; A= write 32-bit to APB ; P= write 32-bit to Access Port register ; ; ; Low level access to CoreSight debug system: ; ------------------------------------------- ; RDP display Debug Port (DP) register ; RAP display Access Port (AP) register ; RDBG [] display core debug register ; WDP modify Debug Port (DP) register ; WAP modify Access Port (AP) register ; WDBG modify core debug register ; MDAPB [] display APB memory ; MMAPB modify APB memory ; MDAHB [] display AHB/AXI memory (32-bit) ; MMAHB modify AHB/AXI memory (32-bit) ; [INIT] ; ; Fill some A64 code into SRAM WM32 0x1d000000 0xd503201f ;nop WM32 0x1d000004 0xd503201f ;nop WM32 0x1d000008 0xd503201f ;nop WM32 0x1d00000c 0xd503201f ;nop WM32 0x1d000010 0xd503201f ;nop WM32 0x1d000014 0xd503201f ;nop WM32 0x1d000018 0xd503201f ;nop WM32 0x1d00001c 0xd503201f ;nop WM32 0x1d000020 0xd503201f ;nop ;WM32 0x1d000020 0xd4400000 ;hlt WM32 0x1d000024 0xd503201f ;nop WM32 0x1d000028 0xd503201f ;nop WM32 0x1d00002c 0xd503201f ;nop WM32 0x1d000030 0xd503201f ;nop WM32 0x1d000034 0xd503201f ;nop WM32 0x1d000038 0xd503201f ;nop WM32 0x1d00003c 0x17fffffb ;b 0x1d000028 ; ; Fill some A32 code into SRAM WM32 0x1d000100 0xe1a00000 ;nop WM32 0x1d000104 0xe1a00000 ;nop WM32 0x1d000108 0xe1a00000 ;nop WM32 0x1d00010c 0xe1a00000 ;nop WM32 0x1d000110 0xe1a00000 ;nop WM32 0x1d000114 0xe1a00000 ;nop WM32 0x1d000118 0xe1a00000 ;nop WM32 0x1d00011c 0xe1a00000 ;nop WM32 0x1d000120 0xe1a00000 ;nop ;WM32 0x1d000120 0xe1000070 ;hlt WM32 0x1d000124 0xe1a00000 ;nop WM32 0x1d000128 0xe1a00000 ;nop WM32 0x1d00012c 0xe1a00000 ;nop WM32 0x1d000130 0xe1a00000 ;nop WM32 0x1d000134 0xe1a00000 ;nop WM32 0x1d000138 0xe1a00000 ;nop WM32 0x1d00013c 0xeafffffb ;b 0x1d000130 ; ; Fill some T32 code into SRAM WM16 0x1d000200 0x46c0 ;nop WM16 0x1d000202 0x46c0 ;nop WM16 0x1d000204 0x46c0 ;nop WM16 0x1d000206 0x46c0 ;nop WM16 0x1d000208 0x46c0 ;nop WM16 0x1d00020a 0x46c0 ;nop WM16 0x1d00020c 0x46c0 ;nop ;WM16 0x1d00020c 0xba80 ;hlt WM16 0x1d00020e 0x46c0 ;nop WM16 0x1d000210 0x46c0 ;nop WM16 0x1d000212 0x46c0 ;nop WM16 0x1d000214 0x46c0 ;nop WM16 0x1d000216 0x46c0 ;nop WM16 0x1d000218 0x46c0 ;nop WM16 0x1d00021a 0x46c0 ;nop WM16 0x1d00021c 0x46c0 ;nop WM16 0x1d00021e 0xe7f8 ;b 0x1d000212 ; [TARGET] POWERUP 3000 ;start delay after power-up detected in ms CLOCK 8000000 ;JTAG clock 8 MHz TRST OPENDRAIN ;TRST driver type (OPENDRAIN | PUSHPULL) RESET NONE ;see SCANINIT ; ; There is no debug communication possible when RESET is asserted. ; In order be able to hard reset the system we use SCANINIT ; and we route a wire from BDI TargetB-13 to J3-2 SCANINIT r1:w1000:t1:w1000:t0: ;assert reset and toggle TRST SCANINIT w10000:r0:w4000000 ;release reset and wait ; ; ; CoreID#0 parameters (active core after reset) #0 CPUTYPE X-GENE 0xfc010000 ;X-Gene CPU 0 ;#0 RESET SOFT ;assert warm reset via EDPCR.CWRR ;#0 STARTUP IDLE ;don't access until attached ;#0 STARTUP WAIT #0 STARTUP HALT ;halt as soon as possible ;#0 STARTUP STOP 7000 ;let U-boot run for 7 seconds ;#0 STARTUP RUN ;let U-boot run #0 ENDIAN LITTLE ;memory model (LITTLE | BIG) #0 VECTOR CATCH RST OSU TDA ;Reset and OS unlock catch, Trap SW access #0 BREAKMODE SOFT ;SOFT or HARD #0 MEMACCESS CORE 10 ;memory access via Core (80 TCK's access delay) ; ; CoreID#1 parameters: #1 CPUTYPE X-GENE 0xfc110000 ;X-Gene CPU 1 ;#1 STARTUP IDLE ;#1 STARTUP WAIT #1 STARTUP RUN #1 ENDIAN LITTLE ;#1 VECTOR CATCH #1 BREAKMODE HARD #1 MEMACCESS CORE 10 ; ; CoreID#2 parameters: #2 CPUTYPE X-GENE 0xfc210000 ;X-Gene CPU 2 ;#2 STARTUP IDLE ;#2 STARTUP WAIT #2 STARTUP RUN #2 ENDIAN LITTLE ;#2 VECTOR CATCH #2 BREAKMODE HARD #2 MEMACCESS CORE 10 ; ; CoreID#3 parameters: #3 CPUTYPE X-GENE 0xfc310000 ;X-Gene CPU 3 ;#3 STARTUP IDLE ;#3 STARTUP WAIT #3 STARTUP RUN #3 ENDIAN LITTLE ;#3 VECTOR CATCH #3 BREAKMODE HARD #3 MEMACCESS CORE 10 ; ; CoreID#4 parameters: #4 CPUTYPE X-GENE 0xfc410000 ;X-Gene CPU 4 ;#4 STARTUP IDLE ;#4 STARTUP WAIT #4 STARTUP RUN #4 ENDIAN LITTLE ;#4 VECTOR CATCH #4 BREAKMODE HARD #4 MEMACCESS CORE 10 ; ; CoreID#5 parameters: #5 CPUTYPE X-GENE 0xfc510000 ;X-Gene CPU 5 ;#5 STARTUP IDLE ;#5 STARTUP WAIT #5 STARTUP RUN #5 ENDIAN LITTLE ;#5 VECTOR CATCH #5 BREAKMODE HARD #5 MEMACCESS CORE 10 ; ; CoreID#6 parameters: #6 CPUTYPE X-GENE 0xfc610000 ;X-Gene CPU 6 ;#6 STARTUP IDLE ;#6 STARTUP WAIT #6 STARTUP RUN #6 ENDIAN LITTLE ;#6 VECTOR CATCH #6 BREAKMODE HARD #6 MEMACCESS CORE 10 ; ; CoreID#7 parameters: #7 CPUTYPE X-GENE 0xfc710000 ;X-Gene CPU 7 ;#7 STARTUP IDLE ;#7 STARTUP WAIT #7 STARTUP RUN #7 ENDIAN LITTLE ;#7 VECTOR CATCH #7 BREAKMODE HARD #7 MEMACCESS CORE 10 ; ; CoreID#8 parameters: Dummy core for AXI accesses #8 CPUTYPE X-GENE #8 STARTUP IDLE #8 MEMACCESS AXI 8 ;memory access via AXI (64 TCK's access delay) ; [HOST] FILE E:\temp\dump256k.bin FORMAT BIN 0x1d001000 ; #0 PROMPT XGENE#0> #1 PROMPT XGENE#1> #2 PROMPT XGENE#2> #3 PROMPT XGENE#3> #4 PROMPT XGENE#4> #5 PROMPT XGENE#5> #6 PROMPT XGENE#6> #7 PROMPT XGENE#7> #8 PROMPT AXI> [FLASH] ; only to test helper code execution WORKSPACE 0x1D000000 CHIPTYPE AM29BX16 CHIPSIZE 0x40000 BUSWIDTH 16 FILE E:/temp/dump16k.bin FORMAT BIN 0x1d010000 [REGS] ;FILE $regARMV8.def FILE $regARMV8-EL2.def