; bdiGDB configuration for HITEX STR912F EVB ; ------------------------------------------ ; [INIT] ; ; Set clock to 48MHz via PLL WM32 0x5C002004 0x000BC019 ;SCU_PLLCONF: PLL=ENA,P=3,N=C0,M=19 DELAY 100 ;let PLL lock WM32 0x5C002000 0x00020000 ;SCU_CLKCNTR: MCLK=PLL ; ; Setup flash memory interface (FMI) WM32 0x54000000 0x00000004 ;FMI_BBSR : boot bank size = 512k WM32 0x5400000C 0x00000000 ;FMI_BBADR : boot bank addr = 0x00000000 WM32 0x54000004 0x00000002 ;FMI_NBBSR : boot bank size = 32k WM32 0x54000010 0x00020000 ;FMI_NBBADR: boot bank addr = 0x00080000 WM32 0x54000018 0x00000018 ;FMI_CR : enable both flash banks ; ; load an execute code to set Configuration Control Register bit 18 WM32 0x40000000 0xee3f0f11 ;mrc 15, 1, r0, cr15, cr1, {0} WM32 0x40000004 0xe3800701 ;orr r0, r0, #262144 ; 0x40000 WM32 0x40000008 0xee2f0f11 ;mcr 15, 1, r0, cr15, cr1, {0} WM32 0x4000000C 0xeafffffe ;b $pc EXEC 0x40000000 ;execute code ; [TARGET] CPUTYPE ARM966E CLOCK 0 ;JTAG clock : use adaptive clocking ;CLOCK 0 7 ;JTAG clock : start with 1 MHz then use adaptive ;CLOCK 6 7 ;JTAG clock : without adaptive clocking cable SCANPRED 1 5 ;TAP #1 Boundary Scan SCANSUCC 1 8 ;TAP #3 Flash Memory ENDIAN LITTLE ;memory model (LITTLE | BIG) VECTOR CATCH 0x1f ;catch D_Abort, P_Abort, SWI, Undef and Reset BREAKMODE HARD ;SOFT or HARD, ARM / Thumb break code WAKEUP 50 [HOST] IP 151.120.25.119 FILE E:\temp\dump512k.bin FORMAT BIN 0x10000000 PROMPT STR912E> [FLASH] WORKSPACE 0x40000000 ;workspace in internal SRAM CHIPTYPE STR910F CHIPSIZE 0x80000 ;512k FILE E:\temp\dump512k.bin FORMAT BIN 0x00000000 ERASE 0x00000000 0x10000 8 UNLOCK ;earse bank 0 ERASE 0x00080000 0x02000 4 UNLOCK ;erase bank 1 [REGS] FILE $regSTR912F.def