;Register definition for FA526 ;=============================== ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; CP15 CP15 register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ; ; CP15 Registers Numbers for FA526: ; ; Via JTAG, CP15 registers are accessed either direct (physical access mode) ; or via interpreted MCR/MRC instructions. ; Read also FA526 manual, part "Debug Support - Scan Chain 15". ; ; Register number for physical access mode (bit 12 = 0): ; ; +-----+-+-----+-+-----+-+-------+ ; |0 0 0|0|0 0 0|i|0 0 0|x| nbr | ; +-----+-+-----+-+-----+-+-------+ ; ; The bit "i" selects the instruction cache (scan chain bit 6), ; the bit "x" extends access to register 15 (scan chain bit 1). ; ; Register number for interpreted access mode (bit 12 = 1): ; +-----+-+-------+-----+-+-------+ ; |opc_2|1| CRm |opc_1|0| nbr | ; +-----+-+-------+-----+-+-------+ ; The 16bit register number is used to build the appropriate MCR/MRC instruction. ; ; ;name type addr size ;------------------------------------------- ; id CP15 0x0000 32 ;ID code cache CP15 0x0100 32 ;Cache type control CP15 0x0001 32 ;Control ttb CP15 0x0002 32 ;Translation Table Base dac CP15 0x0003 32 ;Domain access control dfsr CP15 0x0005 32 ;Data fault status ifsr CP15 0x0105 32 ;Inst fault status far CP15 0x0006 32 ;Fault address dlock CP15 0x0009 32 ;Data lockdown ilock CP15 0x0109 32 ;Instr lockdown tlbidx CP15 0x000a 32 ;TLB index dscratch CP15 0x000b 32 ;Data scratchpad iscratch CP15 0x010b 32 ;Inst scratchpad process CP15 0x000d 32 ;Process ID extctr CP15 0x000e 32 ;Extension control ;