; bdiGDB configuration for Marvell OpenRD board
; ---------------------------------------------
;
; Info about the JTAG clock frequency:
; ------------------------------------
; BDI2000:
;   0=Adaptive,
;   1=16MHz, 2=8MHz, 3=4MHz,
;   4= 1MHz, 5=500kHz, 6=200kHz, 7=100kHz, 8=50kHz,
;   9=20kHz, 10=10kHz, 11=5kHz, 12=2kHz, 13=1kHz
; BDI3000:
;   0=Adaptive,
;   1=32MHz, 2=16MHz, 3=11MHz, 4=8MHz, 5=5MHz, 6=4MHz,
;   7=1MHz, 8=500kHz, 9=200kHz, 10=100kHz, 11=50kHz,
;   12=20kHz, 13=10kHz, 14=5kHz, 15=2kHz, 16=1kHz,
;
;
;
[INIT]
;


[TARGET]
CPUTYPE     FERO926
CLOCK       1 7                 ;BDI3000: start with 1 MHz then use 32 MHz
;CLOCK       1 4                 ;BDI2000: start with 1 MHz then use 16 MHz
TRST        PUSHPULL            ;TRST driver type (OPENDRAIN | PUSHPULL)
POWERUP     2000
WAKEUP      500
RESET	    HARD 500            ;NONE | HARD <n> (ms)
STARTUP     RESET
ENDIAN      LITTLE              ;memory model (LITTLE | BIG)
BREAKMODE   SOFT                ;Use ARM9E BKPT instruction
STEPMODE    HWBP                ;FEROCEON supports only HWBP single step
;VECTOR      CATCH 0x1f          ;catch D_Abort, P_Abort, SWI, Undef and Reset


[HOST]
IP          151.120.25.112
PROMPT      OpenRD>


[FLASH]


[REGS]
DMM1    0xD0000000              ;Internal Address Space
FILE	$reg88F6281.def