; bdiGDB configuration file for AT91SAM9XE-EK
; --------------------------------------------
;
; Info about the JTAG clock frequency:
; ------------------------------------
; BDI2000:
;   0=Adaptive,
;   1=16MHz, 2=8MHz, 3=4MHz,
;   4= 1MHz, 5=500kHz, 6=200kHz, 7=100kHz, 8=50kHz,
;   9=20kHz, 10=10kHz, 11=5kHz, 12=2kHz, 13=1kHz
; BDI3000:
;   0=Adaptive,
;   1=32MHz, 2=16MHz, 3=11MHz, 4=8MHz, 5=5MHz, 6=4MHz,
;   7=1MHz, 8=500kHz, 9=200kHz, 10=100kHz, 11=50kHz,
;   12=20kHz, 13=10kHz, 14=5kHz, 15=2kHz, 16=1kHz,
;
;
; Manual Flash Command via Telnet:
; --------------------------------
; Set   GPNVM[BMS]  :  rm eefc_fcr 0x5a00030b
; Clear GPNVM[BMS]  :  rm eefc_fcr 0x5a00030c
; Get all GPNVM     :  rm eefc_fcr 0x5a00000d;rd eefc_frr
; Get all Lockbits  :  rm eefc_fcr 0x5a00000a;rd eefc_frr
; Get Flash Desc.   :  rm eefc_fcr 0x5a000000;rd eefc_frr;rd eefc_frr;rd eefc_frr;rd eefc_frr
;
;
;
[INIT]
;WREG    CPSR        0x000000D3  ;select supervisor mode
WM32    0xfffffd44  0x00008000  ;Disable watchdog
WM32    0xfffffd08  0xa5000401  ;User reset enable (allows BDI to reset the processor)
;
; Set core at 180 MHz and MCK at 90 MHz
WM32    0xfffffc30  0x00000000  ;Select master slow clock
DELAY   20
WM32    0xfffffc28  0x00003f00  ;Set PLLA default
WM32    0xfffffc2c  0x00007f00  ;Set PLLB default
;
WM32    0xfffffc20  0x00004001  ;PMC_MOR : Enable main oscilator
DELAY   100
WM32    0xfffffc28  0x2057bf09  ;CKGR_PLLAR: Set PLLA to 180 MHz
DELAY   100
WM32    0xfffffc30  0x00000100  ;PMC_MCKR: Select prescaler
DELAY   20
WM32    0xfffffc30  0x00000102  ;PMC_MCKR: Select master clock
DELAY   20
;CLOCK   1                       ;BDI2000: speed-up JTAG clock
CLOCK   2                       ;BDI3000: speed-up JTAG clock
;
; Setup Internal Flash Wait States
WM32    0xfffffa00  0x00000500  ;EEFC_FMR: Flash mode (FWS=5)
;
; SDRAM Configuration
WM32    0xffffef1c  0x0001003a  ;EBI_CSA  : Assign CS1 to SDRAM
WM32    0xFFFFF870  0xFFFF0000  ;PIO_ASR  :
WM32    0xFFFFF874  0x00000000  ;PIO_BSR  :
WM32    0xFFFFF804  0xFFFF0000  ;PIO_PDR  :
;
WM32    0xffffea08  0x85227259  ;SDRAMC_CR: SDRAMC Configuration
WM32    0xffffea00  0x00000001  ;SDRAMC_MR: issue NOP
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000002  ;SDRAMC_MR: issue All Banks Precharge
WM32    0x20000000  0x00000000
DELAY   100
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000003  ;SDRAMC_MR: issue Load Mode Register
WM32    0x20000000  0x00000000
WM32    0xffffea04  0x00000276  ;SDRAMC_TR: SDRAMC Refresh Timer
WM32    0xffffea00  0x00000000  ;SDRAMC_MR: Normal Mode
WM32    0x20000000  0x00000000
;
;WM32    0xffffef00  0x00000003  ;MATRIX_MRCR: map on chip RAM to 0


[TARGET]
POWERUP     2000
CPUTYPE     ARM926E
;CLOCK       1 11                ;BDI2000: start with 5 kHz then use 16 MHz
CLOCK       2 14                ;BDI3000: start with 5 kHz then use 16 MHz
;CLOCK       11                  ;BDI2000: JTAG clock 5 kHz
;CLOCK       14                  ;BDI3000: JTAG clock 5 kHz
;CLOCK       0 11                ;BDI2000 : start with 5 kHz then use adaptive
;CLOCK       0 14                ;BDI3000 : start with 5 kHz then use adaptive
;RESET       HARD 1000
RESET       NONE
STARTUP     RESET
VECTOR      CATCH 0x1e          ;catch D_Abort, P_Abort, SWI, Undef
BREAKMODE   HARD                ;SOFT or HARD, ARM / Thumb break code
;BREAKMODE   SOFT 0xDFFFDFFF     ;SOFT or HARD, ARM / Thumb break code

; Low level JTAG configuration
SCANINIT    r1:t1:w1000:t0:w10000:      ;assert reset and toggle TRST
SCANINIT    w100000:r0:w10000           ;release reset
;
; Between SCANINIT and SCANPOST the ARM ICEBreaker is configured
; and the DBGRQ bit in the ARM debug control register is set.
;
SCANPOST    r1:w10000:r0                ;assert reset, will be catched
;


[HOST]
IP          151.120.25.112
FILE        E:/temp/dump256k.bin
FORMAT      BIN  0x20000000
PROMPT      SAM9XE>      ;new Telnet prompt


[FLASH]
CHIPTYPE    SAM9XE                ;Don't forget to set EEFC_FMR[FWS]
CHIPSIZE    0x80000
BUSWIDTH    32


[REGS]
FILE	$regSAM9XE.def