; bdiGDB configuration file for AT91SAM9261-EK
; --------------------------------------------
;
[INIT]
;
WM32    0xFFFFFD44  0x00008000  ;Disable watchdog
;
; Configure Master clock
WM32    0xfffffc20  0x00004001  ;Enable main oscilator
DELAY   100
WM32    0xfffffc28  0x2060bf09  ;Set PLLA to 200 MHz
DELAY   100
WM32    0xfffffc30  0x00000100  ;Select prescaler
DELAY   20
WM32    0xfffffc30  0x00000102  ;Select master clock
DELAY   20
CLOCK   2                       ;speed-up JTAG clock
;
; PIOC Pin Configuration
WM32    0xfffff870  0xffff0000  ;PIOC_ASR : Port PC31:PC16 as data bus D31:D16
WM32    0xfffff874  0x00000000  ;PIOC_BSR :
WM32    0xfffff804  0xffff0000  ;PIOC_PDR : Disable PIO from controlling PC31:PC16
;
; SDRAM Configuration
WM32    0xffffee30  0x0001003a  ;EBI_CSA  : Assign CS1 to SDRAM
WM32    0xffffea08  0x85227259  ;SDRAMC_CR: SDRAMC Configuration
WM32    0xffffea00  0x00000001  ;SDRAMC_MR: issue NOP
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000002  ;SDRAMC_MR: issue All Banks Precharge
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000004  ;SDRAMC_MR: issue Auto-Refresh
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000003  ;SDRAMC_MR: issue Load Mode Register
WM32    0x20000000  0x00000000
WM32    0xffffea00  0x00000000  ;SDRAMC_MR: Normal Mode
WM32    0x20000000  0x00000000
WM32    0xffffea04  0x00000307  ;SDRAMC_TR: SDRAMC Refresh Timer
;


[TARGET]
CPUTYPE     ARM926E
;CLOCK       14                  ;JTAG clock 5 kHz
CLOCK       2 14                ;JTAG clock : start with 5 kHz then use 16 MHz
;CLOCK       0 14                ;JTAG clock : start with 5 kHz then use adaptive
;CLOCK       0                   ;JTAG clock : adaptive
RESET       NONE
VECTOR      CATCH 0x1e          ;catch D_Abort, P_Abort, SWI, Undef
BREAKMODE   HARD                ;SOFT or HARD, ARM / Thumb break code


; Low level JTAG configuration
SCANINIT    r1:t1:w1000:t0:w10000:      ;assert reset and toggle TRST
SCANINIT    w100000:r0:w10000           ;release reset
;
; Between SCANINIT and SCANPOST the ARM ICEBreaker is configured
; and the DBGRQ bit in the ARM debug control register is set.
;
SCANPOST    r1:w10000:r0:w100000        ;assert reset, will be catched
;


[HOST]
IP          151.120.25.112
FILE        E:/temp/dump256k.bin
FORMAT      BIN  0x20000000
PROMPT      9261>      ;new Telnet prompt


[FLASH]


[REGS]
FILE	$reg9261.def