; bdiGDB configuration for Samsung SMDK40100 evaluation board
; -----------------------------------------------------------
;
[INIT]
;
WM16    0x07FFA002  0xA500      ;BTCON : disable watchdog
;

[TARGET]
CPUTYPE     ARM7TDMI
;CLOCK       1                   ;BDI2000: JTAG clock 16MHz
CLOCK       2                   ;BDI3000: JTAG clock 16MHz
;WAKEUP      3000
;RESET       HARD 1000
STARTUP     STOP 2000           ;let the monitor setup the memory controller.
ENDIAN      BIG                 ;memory model (LITTLE | BIG)
BREAKMODE   HARD                ;SOFT or HARD, ARM / Thumb break code
;BREAKMODE   SOFT 0xDFFFDFFF     ;SOFT or HARD, ARM / Thumb break code
;VECTOR      CATCH 0x1f          ;catch D_Abort, P_Abort, SWI, Undef and Reset
;SIO         7 9600              ;TCP port for serial IO
;DCC         7                   ;TCP port for DCC I/O

[HOST]
IP          151.120.25.119
FILE        E:\cygwin\home\demo\pid7t\fibo.x
FORMAT      ELF
LOAD        MANUAL      ;load VxWorks code MANUAL or AUTO after reset

[FLASH]