; bdiGDB configuration file for CardEngine with ARM720T core
; ----------------------------------------------------------------
; J. Sounggalon S, 05.06.2003
[INIT]
WREG    CPSR        0x000000D3  ;select supervisor mode

[TARGET]
CPUTYPE     ARM720T
;CLOCK       1                   ;BDI2000: JTAG clock 16MHz
CLOCK       2                   ;BDI3000: JTAG clock 16MHz
STARTUP     STOP 5000           ;wait the losh to start up
ENDIAN      LITTLE              ;memory model (LITTLE | BIG)
VECTOR      CATCH               ;catch unhandled exceptions
BREAKMODE   SOFT 0xDFFFDFFF     ;SOFT or HARD, ARM / Thumb break code
DCC         7                   ;TCP port for DCC I/O

[HOST]
IP          151.120.25.119
FILE        E:\cygwin\home\demo\at91\fibo.x
FORMAT      ELF
LOAD        MANUAL
PROMPT      LH79520>

[FLASH]

[REGS]
FILE	E:\cygwin\home\bdidemo\arm\reg720t.def