; bdiGDB configuration file for Cogent CSB337 Board ; ------------------------------------------------- ; [INIT] WCP15 0x010F 0x00002001 ;Enable CP0 and CP13 access delay 10 ;turn on the main oscillator WM32 0xFFFFFC20 0x00000001 delay 100 ; ;turn off PLLA WM32 0xfffffc28 0 delay 100 ; set cpu slow clock ;WM32 0xfffffc30 0x0 delay 100 ; setup plla to 180mhz ; this will give it plenty of time to lock ; while we do other things - cpu is running ; at 32khz for now ; pcm_pllar - diva 2, mula 0x64 184.32mhz WM32 0xfffffc28 0x20633E02 delay 100 ;set MCK to PLLA/4 WM32 0xfffffc30 0x00000302 delay 500 ; ; enable the peripheral clock on pb27 ; first enable it in the clock registers ; pcm_scer: enable pck0 WM32 0xfffffc00 0x0000ff00 delay 1 ; pcm_pcer: enable all peripheral clocks WM32 0xfffffc10 0xffffffff delay 1 ; pmc_pck0: set pck0 master plla/4 WM32 0xfffffc40 0x0000000a ; enable d16-31 on portc to be alternate function a (databus) ; also enable *wait (pc6) ; portc a function, pc6 wait function a WM32 0xfffff804 0xffff0000 delay 1 WM32 0xfffff800 0x0000ffff delay 1 WM32 0xfffff870 0xffff0000 delay 1 WM32 0xfffff814 0xffffffff delay 1 ; enable ethernet and DTXD/DRXD on Port A ; ethernet PA16-7, DTXD PA31 WM32 0xfffff470 0xC001FF80 delay 1 WM32 0xfffff404 0xC001FF80 delay 1 ; PIO_PDR: PB27 peripheral, PB19-12 Ethernet, all else GPIO WM32 0xfffff604 0x080ff000 delay 1 WM32 0xfffff600 0xf7f00fff delay 1 WM32 0xfffff670 0x08000000 delay 1 WM32 0xfffff674 0x000ff000 delay 1 WM32 0xfffff610 0x00000007 delay 1 WM32 0xfffff630 0x00000007 delay 1 WM32 0xfffff634 0x00000004 delay 1 ; assign sdram_cs to cs1, all others to sram ;ebi_csa: cs1 sdram WM32 0xffffff60 0x00000002 delay 1 ;ebi_cfg: disable databus pullup and bus sharing WM32 0xffffff64 0x00000001 delay 1 ;write cs0 for 16-bits, 10 wait states WM32 0xffffff70 0x1100318a delay 1 ; write sdram configuration register, for cas latency 2, ; ras to cas 2, 32-bit, 4 bank, 9 column, 12 row addresses WM32 0xffffff98 0x2188C155 delay 1 ; setup sdram - all sdram timing is off mclk ; sdramc_mr: issue nop WM32 0xffffff90 0x00000001 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 10 ; sdramc_mr: issue precharge all WM32 0xffffff90 0x00000002 delay 1 WM32 0x20000000 0 delay 10 ; force 8 refresh cycles ; sdramc_mr: issue refresh WM32 0xffffff90 0x00000004 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 10 ; set mrs mode WM32 0xffffff90 0x00000003 delay 1 WM32 0x20000080 0 delay 10 ; now set refresh to the final number of ~15usec WM32 0xffffff94 0x00000100 delay 1 WM32 0x20000000 0 delay 10 ; set normal mode WM32 0xffffff90 0x00000000 delay 1 WM32 0x20000000 0 delay 10 [TARGET] CPUTYPE ARM920T ARM ;the target CPU type CLOCK 2 8 ;JTAG clock divider ;CLOCK 2 8 ;BDI2000: JTAG clock 8MHz / 50kHz CLOCK 4 11 ;BDI3000: JTAG clock 8MHz / 50kHz ENDIAN LITTLE ;memory model (LITTLE | BIG) BREAKMODE HARD ;SOFT or HARD VECTOR CATCH ;trap all vectors STARTUP RESET [HOST] IP 192.168.254.106 FILE c:\umon\targets\csb337\monitor\csb337_tst.bin FORMAT BIN 0x20100000 ; external SDRAM ;FORMAT BIN 0x200000 ; internal SRAM LOAD MANUAL ;load code code MANUAL or AUTO after reset PROMPT CSB337_BDI> [FLASH] ;WORKSPACE 0x00200000 ;workspace in internal RAM for fast programming algorithm WORKSPACE 0x20200000 ;workspace in SDRAM for fast programming algorithm CHIPTYPE STRATAX16 ;Flash type CHIPSIZE 0x2000000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) FILE c:\umon\targets\csb337\monitor\csb337_rom.bin ;FILE C:\umon\targets\csb337_wince\monitor\csb337_rom.bin FORMAT BIN 0x10000000 ERASE 0x10000000 ERASE 0x10020000 ERASE 0x10080000 [REGS] FILE c:\abatron\arm7_9\reg920t.def