;Register definition for ARM926E
;===============================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CP15	CP15 register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
;
; CP15 Registers
;
;  Register Numbers for 926E:
;  +-------+-------+-------+-------+
;  | | | | | | | | | | | | | | | | |
;  +-+-----+-+-----+-------+-------+
;  |-|opc_1|-|opc_2|  CRm  |  nbr  |
;  +-+-----+-+-----+-------+-------+
;
;
id		CP15    0x0000          32      ;ID code
cache   	CP15    0x0100          32      ;Cache type
tcm             CP15    0x0200          32      ;TCM status
control 	CP15    0x0001          32      ;Control
ttb     	CP15    0x0002          32      ;Translation table base
dac     	CP15    0x0003          32      ;Domain access control
dfsr      	CP15    0x0005          32      ;Data fault status
ifsr    	CP15    0x0105          32      ;Inst fault status
far       	CP15    0x0006          32      ;Fault address
;
fcsr      	CP15    0x000d          32      ;Fast context switch PID
context 	CP15    0x010d          32      ;Context ID
;


