;Register definition for AT91RM9200
;==================================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CP15	CP15 register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;
; CP15 Registers Numbers for 920T:
;
; Via JTAG, CP15 registers are accessed either direct (physical access mode)
; or via interpreted MCR/MRC instructions.
; Read also ARM920T manual, part "Debug Support - Scan Chain 15".
;
; Register number for physical access mode (bit 12 = 0):
;
;       +-----+-+-----+-+-----+-+-------+
;       |0 0 0|0|0 0 0|i|0 0 0|x|  nbr  |
;       +-----+-+-----+-+-----+-+-------+
;
; The bit "i" selects the instruction cache (scan chain bit 33), the bit "x" extends access to register 15
; (scan chain bit 38).
;
; Register number for interpreted access mode (bit 12 = 1):
;       +-----+-+-------+-----+-+-------+
;       |opc_2|1|  CRm  |opc_1|0|  nbr  |
;       +-----+-+-------+-----+-+-------+
; The 16bit register number is used to build the appropriate MCR/MRC instruction.
;
;
;name		type	addr		size
;-------------------------------------------
;
id		CP15    0x0000          32      ;ID code
cache   	CP15    0x0100          32      ;Cache type
control 	CP15    0x0001          32      ;Control
dlock   	CP15    0x0009          32      ;data lockdown register
ilock   	CP15    0x0109          32      ;instruction lockdown register
process   	CP15    0x000d          32      ;process ID
;
;wittb     	CP15    0x51af          32      ;write inst TTB
rittb     	CP15    0x51af          32      ;read  inst TTB
;wdttb     	CP15    0x52af          32      ;write data TTB
rdttb     	CP15    0x12a2          32      ;read  data TTB
;
;widac     	CP15    0x71af          32      ;write inst DAC
ridac     	CP15    0x71af          32      ;read  inst DAC
;wddac     	CP15    0x72af          32      ;write data DAC
rddac     	CP15    0x1003          32      ;read  data DAC
;
ifsr     	CP15    0x3005          32      ;read/write inst FSR
dfsr     	CP15    0x1005          32      ;read/write data FSR
;
ifar     	CP15    0x3006          32      ;read/write inst FAR
dfar     	CP15    0x1006          32      ;read/write data FAR
;
;
; Memory Controller (MC)
;
mc_rcr	        MM	0xFFFFFF00	32      ;MC Remap Control Register
mc_asr	        MM	0xFFFFFF04	32      ;MC Abort Status Register
mc_aasr	        MM	0xFFFFFF08	32      ;MC Abort Address Status Register
mc_mpr 	        MM	0xFFFFFF0C	32      ;MC Master Priority Register
;
; External Bus Interface (EBI)
;
ebi_csa 	MM	0xFFFFFF60	32      ;Chip Select Assignment Register
ebi_cfgr	MM	0xFFFFFF64	32      ;Configuration Register
;
; Static Memory Controller (SMC)
;
smc_csr0	MM	0xFFFFFF70	32      ;SMC Chip Select Register 0
smc_csr1	MM	0xFFFFFF74	32      ;SMC Chip Select Register 1
smc_csr2	MM	0xFFFFFF78	32      ;SMC Chip Select Register 2
smc_csr3	MM	0xFFFFFF7C	32      ;SMC Chip Select Register 3
smc_csr4	MM	0xFFFFFF80	32      ;SMC Chip Select Register 4
smc_csr5	MM	0xFFFFFF84	32      ;SMC Chip Select Register 5
smc_csr6	MM	0xFFFFFF88	32      ;SMC Chip Select Register 6
smc_csr7	MM	0xFFFFFF8C	32      ;SMC Chip Select Register 7
;
; SDRAM Controller (SDRAMC)
;
sdramc_mr 	MM	0xFFFFFF90	32      ;SDRAMC Mode Register
sdramc_tr 	MM	0xFFFFFF94	32      ;SDRAMC Refresh Timer Register
sdramc_cr 	MM	0xFFFFFF98	32      ;SDRAMC Configuration Register
sdramc_srr	MM	0xFFFFFF9C	32      ;SDRAMC Self Refresh Register
sdramc_lpr	MM	0xFFFFFFA0	32      ;SDRAMC Low Power Register
sdramc_ier	MM	0xFFFFFFA4	32      ;SDRAMC Interrupt Enable Register
sdramc_idr	MM	0xFFFFFFA8	32      ;SDRAMC Interrupt Disable Register
sdramc_imr	MM	0xFFFFFFAC	32      ;SDRAMC Interrupt Mask Register
sdramc_isr	MM	0xFFFFFFB0	32      ;SDRAMC Interrupt Status Register
;
; Burst Flash Controller (BFC)
;
bfc_mr 	        MM	0xFFFFFFC0	32      ;Burst Flash Controller Mode Register
;
; Advanced Interrupt Controller (AIC)
;
aic_smr0        MM	0xFFFFF000	32      ;Source Mode Registers
aic_smr1        MM	0xFFFFF004	32
aic_smr2        MM	0xFFFFF008	32
aic_smr3        MM	0xFFFFF00C	32
aic_smr4        MM	0xFFFFF010	32
aic_smr5        MM	0xFFFFF014	32
aic_smr6        MM	0xFFFFF018	32
aic_smr7        MM	0xFFFFF01C	32
aic_smr8        MM	0xFFFFF020	32
aic_smr9        MM	0xFFFFF024	32
aic_smr10       MM	0xFFFFF028	32
aic_smr11       MM	0xFFFFF02C	32
aic_smr12       MM	0xFFFFF030	32
aic_smr13       MM	0xFFFFF034	32
aic_smr14       MM	0xFFFFF038	32
aic_smr15       MM	0xFFFFF03C	32
aic_smr16       MM	0xFFFFF040	32
aic_smr17       MM	0xFFFFF044	32
aic_smr18       MM	0xFFFFF048	32
aic_smr19       MM	0xFFFFF04C	32
aic_smr20       MM	0xFFFFF050	32
aic_smr21       MM	0xFFFFF054	32
aic_smr22       MM	0xFFFFF058	32
aic_smr23       MM	0xFFFFF05C	32
aic_smr24       MM	0xFFFFF060	32
aic_smr25       MM	0xFFFFF064	32
aic_smr26       MM	0xFFFFF068	32
aic_smr27       MM	0xFFFFF06C	32
aic_smr28       MM	0xFFFFF070	32
aic_smr29       MM	0xFFFFF074	32
aic_smr30       MM	0xFFFFF078	32
aic_smr31       MM	0xFFFFF07C	32
;
aic_svr0        MM	0xFFFFF080	32      ;Source Vector Registers
aic_svr1        MM	0xFFFFF084	32
aic_svr2        MM	0xFFFFF088	32
aic_svr3        MM	0xFFFFF08C	32
aic_svr4        MM	0xFFFFF090	32
aic_svr5        MM	0xFFFFF094	32
aic_svr6        MM	0xFFFFF098	32
aic_svr7        MM	0xFFFFF09C	32
aic_svr8        MM	0xFFFFF0A0	32
aic_svr9        MM	0xFFFFF0A4	32
aic_svr10       MM	0xFFFFF0A8	32
aic_svr11       MM	0xFFFFF0AC	32
aic_svr12       MM	0xFFFFF0B0	32
aic_svr13       MM	0xFFFFF0B4	32
aic_svr14       MM	0xFFFFF0B8	32
aic_svr15       MM	0xFFFFF0BC	32
aic_svr16       MM	0xFFFFF0C0	32
aic_svr17       MM	0xFFFFF0C4	32
aic_svr18       MM	0xFFFFF0C8	32
aic_svr19       MM	0xFFFFF0CC	32
aic_svr20       MM	0xFFFFF0D0	32
aic_svr21       MM	0xFFFFF0D4	32
aic_svr22       MM	0xFFFFF0D8	32
aic_svr23       MM	0xFFFFF0DC	32
aic_svr24       MM	0xFFFFF0E0	32
aic_svr25       MM	0xFFFFF0E4	32
aic_svr26       MM	0xFFFFF0E8	32
aic_svr27       MM	0xFFFFF0EC	32
aic_svr28       MM	0xFFFFF0F0	32
aic_svr29       MM	0xFFFFF0F4	32
aic_svr30       MM	0xFFFFF0F8	32
aic_svr31       MM	0xFFFFF0FC	32
;
aic_ivr         MM	0xFFFFF100	32      ;Interrupt Vector Register
aic_fvr         MM	0xFFFFF104	32      ;Fast Interrupt Vector Register
aic_isr         MM	0xFFFFF108	32      ;Interrupt Status Register
aic_ipr         MM	0xFFFFF10C	32      ;Interrupt Pending Register
aic_imr         MM	0xFFFFF110	32      ;Interrupt Mask Register
aic_cisr        MM	0xFFFFF114	32      ;Core Interrupt Status Register
aic_iecr        MM	0xFFFFF120	32      ;Interrupt Enable Command Register
aic_idcr        MM	0xFFFFF124	32      ;Interrupt Disable Command Register
aic_iccr        MM	0xFFFFF128	32      ;Interrupt Clear Command Register
aic_iscr        MM	0xFFFFF12C	32      ;Interrupt Set Command Register
aic_eoicr       MM	0xFFFFF130	32      ;End of Interrupt Command Register
aic_spu         MM	0xFFFFF134	32      ;Spurious Interrupt Vector Register
aic_dcr         MM	0xFFFFF138	32      ;Debug Control Register
aic_ffer        MM	0xFFFFF140	32      ;Fast Forcing Enable Register
aic_ffdr        MM	0xFFFFF144	32      ;Fast Forcing Disable Register
aic_ffsr        MM	0xFFFFF148	32      ;Fast Forcing Status Register
;
; Power Management Controller (PMC)
;
pmc_scer        MM	0xFFFFFC00	32      ;System Clock Enable Register
pmc_scdr        MM	0xFFFFFC04	32      ;System Clock Disable Register
pmc_scsr        MM	0xFFFFFC08	32      ;System Clock Status Register
pmc_pcer        MM	0xFFFFFC10	32      ;Peripheral Clock Enable Register
pmc_pcdr        MM	0xFFFFFC14	32      ;Peripheral Clock Disable Register
pmc_pcsr        MM	0xFFFFFC18	32      ;Peripheral Clock Status Register
pmc_mor         MM	0xFFFFFC20	32      ;Main Oscillator Register
pmc_mcfr        MM	0xFFFFFC24	32      ;Main Clock Frequency Register
pmc_pllar       MM	0xFFFFFC28	32      ;PLL A Register
pmc_pllbr       MM	0xFFFFFC2C	32      ;PLL B Register
pmc_mckr        MM	0xFFFFFC30	32      ;Master Clock Register
pmc_pck0        MM	0xFFFFFC40	32      ;Programmable Clock 0 Register
pmc_pck1        MM	0xFFFFFC44	32      ;Programmable Clock 1 Register
pmc_pck2        MM	0xFFFFFC48	32      ;Programmable Clock 2 Register
pmc_pck3        MM	0xFFFFFC4C	32      ;Programmable Clock 3 Register
pmc_pck4        MM	0xFFFFFC50	32      ;Programmable Clock 4 Register
pmc_pck5        MM	0xFFFFFC54	32      ;Programmable Clock 5 Register
pmc_pck6        MM	0xFFFFFC58	32      ;Programmable Clock 6 Register
pmc_pck7        MM	0xFFFFFC5C	32      ;Programmable Clock 7 Register
pmc_ier         MM	0xFFFFFC60	32      ;Interrupt Enable Register
pmc_idr         MM	0xFFFFFC64	32      ;Interrupt Disable Register
pmc_sr          MM	0xFFFFFC68	32      ;Status Register
pmc_imr         MM	0xFFFFFC6C	32      ;Interrupt Mask Register
;
; System Timer (ST)
;
st_cr           MM	0xFFFFFD00	32      ;Control Register
st_pimr         MM	0xFFFFFD04	32      ;Period Interval Mode Register
st_wdmr         MM	0xFFFFFD08	32      ;Watchdog Mode Register
st_rtmr         MM	0xFFFFFD0C	32      ;Real-time Mode Register
st_sr           MM	0xFFFFFD10	32      ;Status Register
st_ier          MM	0xFFFFFD14	32      ;Interrupt Enable Register
st_idr          MM	0xFFFFFD18	32      ;Interrupt Disable Register
st_imr          MM	0xFFFFFD1C	32      ;Interrupt Mask Register
st_rtar         MM	0xFFFFFD20	32      ;Real-time Alarm Register
st_crtr         MM	0xFFFFFD24	32      ;Current Real-time Register
;
; Real Time Controller (RTC)
;
rtc_cr          MM	0xFFFFFE00	32      ;RTC Control Register
rtc_mr          MM	0xFFFFFE04	32      ;RTC Mode Register
rtc_timr        MM	0xFFFFFE08	32      ;RTC Time Register
rtc_calr        MM	0xFFFFFE0C	32      ;RTC Calendar Register
rtc_timalr      MM	0xFFFFFE10	32      ;RTC Time Alarm Register
rtc_calalr      MM	0xFFFFFE14	32      ;RTC Calendar Alarm Register
rtc_sr          MM	0xFFFFFE18	32      ;RTC Status Register
rtc_sccr        MM	0xFFFFFE1C	32      ;RTC Status Clear Command Register
rtc_ier         MM	0xFFFFFE20	32      ;RTC Interrupt Enable Register
rtc_idr         MM	0xFFFFFE24	32      ;RTC Interrupt Disable Register
rtc_imr         MM	0xFFFFFE28	32      ;RTC Interrupt Mask Register
rtc_ver         MM	0xFFFFFE2C	32      ;RTC Valid Entry Register
;
; Debug Unit (DBGU)
;
dbgu_cr         MM	0xFFFFF200	32      ;Control Register
dbgu_mr         MM	0xFFFFF204	32      ;Mode Register
dbgu_ier        MM	0xFFFFF208	32      ;Interrupt Enable Register
dbgu_idr        MM	0xFFFFF20C	32      ;Interrupt Disable Register
dbgu_imr        MM	0xFFFFF210	32      ;Interrupt Mask Register
dbgu_sr         MM	0xFFFFF214	32      ;Status Register
dbgu_rhr        MM	0xFFFFF218	32      ;Receive Holding Register
dbgu_thr        MM	0xFFFFF21C	32      ;Transmit Holding Register
dbgu_brgr       MM	0xFFFFF220	32      ;Baud Rate Generator Register
dbgu_cidr       MM	0xFFFFF240	32      ;Chip ID Register
dbgu_exid       MM	0xFFFFF244	32      ;Chip ID Extension Register
dbgu_fnr        MM	0xFFFFF248	32      ;Force NTRST Register
;
; Parallel Input/Output Controller (PIO)
;
pioa_per        MM	0xFFFFF400	32      ;PIO Enable Register
pioa_pdr        MM	0xFFFFF404	32      ;PIO Disable Register
pioa_psr        MM	0xFFFFF408	32      ;PIO Status Register (1)
pioa_oer        MM	0xFFFFF410	32      ;PIO Output Enable Register
pioa_odr        MM	0xFFFFF414	32      ;PIO Output Disable Register
pioa_osr        MM	0xFFFFF418	32      ;PIO Output Status Register
pioa_ifer       MM	0xFFFFF420	32      ;PIO Glitch Input Filter Enable Register
pioa_ifdr       MM	0xFFFFF424	32      ;PIO Glitch Input Filter Disable Register
pioa_ifsr       MM	0xFFFFF428	32      ;PIO Glitch Input Filter Status Register
pioa_sodr       MM	0xFFFFF430	32      ;PIO Set Output Data Register
pioa_codr       MM	0xFFFFF434	32      ;PIO Clear Output Data Register
pioa_odsr       MM	0xFFFFF438	32      ;PIO Output Data Status Register(2)
pioa_pdsr       MM	0xFFFFF43C	32      ;PIO Pin Data Status Register(3)
pioa_ier        MM	0xFFFFF440	32      ;PIO Interrupt Enable Register
pioa_idr        MM	0xFFFFF444	32      ;PIO Interrupt Disable Register
pioa_imr        MM	0xFFFFF448	32      ;PIO Interrupt Mask Register
pioa_isr        MM	0xFFFFF44C	32      ;PIO Interrupt Status Register(4)
pioa_mder       MM	0xFFFFF450	32      ;PIO Multi-driver Enable Register
pioa_mddr       MM	0xFFFFF454	32      ;PIO Multi-driver Disable Register
pioa_mdsr       MM	0xFFFFF458	32      ;PIO Multi-driver Status Register
pioa_pudr       MM	0xFFFFF460	32      ;PIO Pull-up Disable Register
pioa_puer       MM	0xFFFFF464	32      ;PIO Pull-up Enable Register
pioa_pusr       MM	0xFFFFF468	32      ;PIO Pad Pull-up Status Register
pioa_asr        MM	0xFFFFF470	32      ;PIO Peripheral A Select Register(5)
pioa_bsr        MM	0xFFFFF474	32      ;PIO Peripheral B Select Register(5)
pioa_absr       MM	0xFFFFF478	32      ;PIO AB Status Register(5)
pioa_ower       MM	0xFFFFF4A0	32      ;PIO Output Write Enable
pioa_owdr       MM	0xFFFFF4A4	32      ;PIO Output Write Disable
pioa_owsr       MM	0xFFFFF4A8	32      ;PIO Output Write Status Register
;
piob_per        MM	0xFFFFF600	32      ;PIOB
piob_pdr        MM	0xFFFFF604	32
piob_psr        MM	0xFFFFF608	32
piob_oer        MM	0xFFFFF610	32
piob_odr        MM	0xFFFFF614	32
piob_osr        MM	0xFFFFF618	32
piob_ifer       MM	0xFFFFF620	32
piob_ifdr       MM	0xFFFFF624	32
piob_ifsr       MM	0xFFFFF628	32
piob_sodr       MM	0xFFFFF630	32
piob_codr       MM	0xFFFFF634	32
piob_odsr       MM	0xFFFFF638	32
piob_pdsr       MM	0xFFFFF63C	32
piob_ier        MM	0xFFFFF640	32
piob_idr        MM	0xFFFFF644	32
piob_imr        MM	0xFFFFF648	32
piob_isr        MM	0xFFFFF64C	32
piob_mder       MM	0xFFFFF650	32
piob_mddr       MM	0xFFFFF654	32
piob_mdsr       MM	0xFFFFF658	32
piob_pudr       MM	0xFFFFF660	32
piob_puer       MM	0xFFFFF664	32
piob_pusr       MM	0xFFFFF668	32
piob_asr        MM	0xFFFFF670	32
piob_bsr        MM	0xFFFFF674	32
piob_absr       MM	0xFFFFF678	32
piob_ower       MM	0xFFFFF6A0	32
piob_owdr       MM	0xFFFFF6A4	32
piob_owsr       MM	0xFFFFF6A8	32
;
pioc_per        MM	0xFFFFF800	32      ;PIOC
pioc_pdr        MM	0xFFFFF804	32
pioc_psr        MM	0xFFFFF808	32
pioc_oer        MM	0xFFFFF810	32
pioc_odr        MM	0xFFFFF814	32
pioc_osr        MM	0xFFFFF818	32
pioc_ifer       MM	0xFFFFF820	32
pioc_ifdr       MM	0xFFFFF824	32
pioc_ifsr       MM	0xFFFFF828	32
pioc_sodr       MM	0xFFFFF830	32
pioc_codr       MM	0xFFFFF834	32
pioc_odsr       MM	0xFFFFF838	32
pioc_pdsr       MM	0xFFFFF83C	32
pioc_ier        MM	0xFFFFF840	32
pioc_idr        MM	0xFFFFF844	32
pioc_imr        MM	0xFFFFF848	32
pioc_isr        MM	0xFFFFF84C	32
pioc_mder       MM	0xFFFFF850	32
pioc_mddr       MM	0xFFFFF854	32
pioc_mdsr       MM	0xFFFFF858	32
pioc_pudr       MM	0xFFFFF860	32
pioc_puer       MM	0xFFFFF864	32
pioc_pusr       MM	0xFFFFF868	32
pioc_asr        MM	0xFFFFF870	32
pioc_bsr        MM	0xFFFFF874	32
pioc_absr       MM	0xFFFFF878	32
pioc_ower       MM	0xFFFFF8A0	32
pioc_owdr       MM	0xFFFFF8A4	32
pioc_owsr       MM	0xFFFFF8A8	32
;
piod_per        MM	0xFFFFFA00	32      ;PIOD
piod_pdr        MM	0xFFFFFA04	32
piod_psr        MM	0xFFFFFA08	32
piod_oer        MM	0xFFFFFA10	32
piod_odr        MM	0xFFFFFA14	32
piod_osr        MM	0xFFFFFA18	32
piod_ifer       MM	0xFFFFFA20	32
piod_ifdr       MM	0xFFFFFA24	32
piod_ifsr       MM	0xFFFFFA28	32
piod_sodr       MM	0xFFFFFA30	32
piod_codr       MM	0xFFFFFA34	32
piod_odsr       MM	0xFFFFFA38	32
piod_pdsr       MM	0xFFFFFA3C	32
piod_ier        MM	0xFFFFFA40	32
piod_idr        MM	0xFFFFFA44	32
piod_imr        MM	0xFFFFFA48	32
piod_isr        MM	0xFFFFFA4C	32
piod_mder       MM	0xFFFFFA50	32
piod_mddr       MM	0xFFFFFA54	32
piod_mdsr       MM	0xFFFFFA58	32
piod_pudr       MM	0xFFFFFA60	32
piod_puer       MM	0xFFFFFA64	32
piod_pusr       MM	0xFFFFFA68	32
piod_asr        MM	0xFFFFFA70	32
piod_bsr        MM	0xFFFFFA74	32
piod_absr       MM	0xFFFFFA78	32
piod_ower       MM	0xFFFFFAA0	32
piod_owdr       MM	0xFFFFFAA4	32
piod_owsr       MM	0xFFFFFAA8	32
;
; Serial Peripheral Interface (SPI)
;
spi_cr          MM	0xFFFE0000	32      ;Control Register
spi_mr          MM	0xFFFE0004	32      ;Mode Register
spi_rdr         MM	0xFFFE0008	32      ;Receive Data Register
spi_tdr         MM	0xFFFE000C	32      ;Transmit Data Register
spi_sr          MM	0xFFFE0010	32      ;Status Register
spi_ier         MM	0xFFFE0014	32      ;Interrupt Enable Register
spi_idr         MM	0xFFFE0018	32      ;Interrupt Disable Register
spi_imr         MM	0xFFFE001C	32      ;Interrupt Mask Register
spi_csr0        MM	0xFFFE0030	32      ;Chip Select Register 0
spi_csr1        MM	0xFFFE0034	32      ;Chip Select Register 1
spi_csr2        MM	0xFFFE0038	32      ;Chip Select Register 2
spi_csr3        MM	0xFFFE003C	32      ;Chip Select Register 3
;
; Two-wire Interface (TWI)
;
twi_cr          MM	0xFFFB8000	32      ;Control Register
twi_mmr         MM	0xFFFB8004	32      ;Master Mode Register
twi_iadr        MM	0xFFFB800C	32      ;Internal Address Register
twi_cwgr        MM	0xFFFB8010	32      ;Clock Waveform Generator Register
twi_sr          MM	0xFFFB8020	32      ;Status Register
twi_ier         MM	0xFFFB8024	32      ;Interrupt Enable Register
twi_idr         MM	0xFFFB8028	32      ;Interrupt Disable Register
twi_imr         MM	0xFFFB802C	32      ;Interrupt Mask Register
twi_rhr         MM	0xFFFB8030	32      ;Receive Holding Register
twi_thr         MM	0xFFFB8034	32      ;Transmit Holding Register
;
; USART (US)
;
us0_cr          MM	0xFFFC0000	32      ;Control Register
us0_mr          MM	0xFFFC0004	32      ;Mode Register
us0_ier         MM	0xFFFC0008	32      ;Interrupt Enable Register
us0_idr         MM	0xFFFC000C	32      ;Interrupt Disable Register
us0_imr         MM	0xFFFC0010	32      ;Interrupt Mask Register
us0_csr         MM	0xFFFC0014	32      ;Channel Status Register
us0_rhr         MM	0xFFFC0018	32      ;Receiver Holding Register
us0_thr         MM	0xFFFC001C	32      ;Transmitter Holding Register
us0_brgr        MM	0xFFFC0020	32      ;Baud Rate Generator Register
us0_rtor        MM	0xFFFC0024	32      ;Receiver Time-out Register
us0_ttgr        MM	0xFFFC0028	32      ;Transmitter Timeguard Register
us0_fidi        MM	0xFFFC0040	32      ;FI DI Ratio Register
us0_ner         MM	0xFFFC0044	32      ;Number of Errors Register
us0_if          MM	0xFFFC004C	32      ;IrDA Filter Register
;
us1_cr          MM	0xFFFC4000	32      ;USART1
us1_mr          MM	0xFFFC4004	32
us1_ier         MM	0xFFFC4008	32
us1_idr         MM	0xFFFC400C	32
us1_imr         MM	0xFFFC4010	32
us1_csr         MM	0xFFFC4014	32
us1_rhr         MM	0xFFFC4018	32
us1_thr         MM	0xFFFC401C	32
us1_brgr        MM	0xFFFC4020	32
us1_rtor        MM	0xFFFC4024	32
us1_ttgr        MM	0xFFFC4028	32
us1_fidi        MM	0xFFFC4040	32
us1_ner         MM	0xFFFC4044	32
us1_if          MM	0xFFFC404C	32
;
us2_cr          MM	0xFFFC8000	32      ;USART2
us2_mr          MM	0xFFFC8004	32
us2_ier         MM	0xFFFC8008	32
us2_idr         MM	0xFFFC800C	32
us2_imr         MM	0xFFFC8010	32
us2_csr         MM	0xFFFC8014	32
us2_rhr         MM	0xFFFC8018	32
us2_thr         MM	0xFFFC801C	32
us2_brgr        MM	0xFFFC8020	32
us2_rtor        MM	0xFFFC8024	32
us2_ttgr        MM	0xFFFC8028	32
us2_fidi        MM	0xFFFC8040	32
us2_ner         MM	0xFFFC8044	32
us2_if          MM	0xFFFC804C	32
;
us3_cr          MM	0xFFFCC000	32      ;USART3
us3_mr          MM	0xFFFCC004	32
us3_ier         MM	0xFFFCC008	32
us3_idr         MM	0xFFFCC00C	32
us3_imr         MM	0xFFFCC010	32
us3_csr         MM	0xFFFCC014	32
us3_rhr         MM	0xFFFCC018	32
us3_thr         MM	0xFFFCC01C	32
us3_brgr        MM	0xFFFCC020	32
us3_rtor        MM	0xFFFCC024	32
us3_ttgr        MM	0xFFFCC028	32
us3_fidi        MM	0xFFFCC040	32
us3_ner         MM	0xFFFCC044	32
us3_if          MM	0xFFFCC04C	32
;
; Serial Synchronous Controller (SSC)
;
ssc0_cr         MM	0xFFFD0000	32      ;Control Register
ssc0_cmr        MM	0xFFFD0004	32      ;Clock Mode Register
ssc0_rcmr       MM	0xFFFD0010	32      ;Receive Clock Mode Register
ssc0_rfmr       MM	0xFFFD0014	32      ;Receive Frame Mode Register
ssc0_tcmr       MM	0xFFFD0018	32      ;Transmit Clock Mode Register
ssc0_tfmr       MM	0xFFFD001C	32      ;Transmit Frame Mode Register
ssc0_rhr        MM	0xFFFD0020	32      ;Receive Holding Register
ssc0_thr        MM	0xFFFD0024	32      ;Transmit Holding Register
ssc0_rshr       MM	0xFFFD0030	32      ;Receive Sync. Holding Register
ssc0_tshr       MM	0xFFFD0034	32      ;Transmit Sync. Holding Register
ssc0_sr         MM	0xFFFD0040	32      ;Status Register
ssc0_ier        MM	0xFFFD0044	32      ;Interrupt Enable Register
ssc0_idr        MM	0xFFFD0048	32      ;Interrupt Disable Register
ssc0_imr        MM	0xFFFD004C	32      ;Interrupt Mask Register
;
ssc1_cr         MM	0xFFFD4000	32      ;SSC1
ssc1_cmr        MM	0xFFFD4004	32
ssc1_rcmr       MM	0xFFFD4010	32
ssc1_rfmr       MM	0xFFFD4014	32
ssc1_tcmr       MM	0xFFFD4018	32
ssc1_tfmr       MM	0xFFFD401C	32
ssc1_rhr        MM	0xFFFD4020	32
ssc1_thr        MM	0xFFFD4024	32
ssc1_rshr       MM	0xFFFD4030	32
ssc1_tshr       MM	0xFFFD4034	32
ssc1_sr         MM	0xFFFD4040	32
ssc1_ier        MM	0xFFFD4044	32
ssc1_idr        MM	0xFFFD4048	32
ssc1_imr        MM	0xFFFD404C	32
;
ssc2_cr         MM	0xFFFD8000	32      ;SSC2
ssc2_cmr        MM	0xFFFD8004	32
ssc2_rcmr       MM	0xFFFD8010	32
ssc2_rfmr       MM	0xFFFD8014	32
ssc2_tcmr       MM	0xFFFD8018	32
ssc2_tfmr       MM	0xFFFD801C	32
ssc2_rhr        MM	0xFFFD8020	32
ssc2_thr        MM	0xFFFD8024	32
ssc2_rshr       MM	0xFFFD8030	32
ssc2_tshr       MM	0xFFFD8034	32
ssc2_sr         MM	0xFFFD8040	32
ssc2_ier        MM	0xFFFD8044	32
ssc2_idr        MM	0xFFFD8048	32
ssc2_imr        MM	0xFFFD804C	32
;
; Timer Counter 0,1,2 (TC)
;
tc0_ccr         MM	0xFFFA0000	32      ;Channel Control Register
tc0_cmr         MM	0xFFFA0004	32      ;Channel Mode Register
tc0_cv          MM	0xFFFA0010	32      ;Counter Value
tc0_ra          MM	0xFFFA0014	32      ;Register A
tc0_rb          MM	0xFFFA0018	32      ;Register B
tc0_rc          MM	0xFFFA001C	32      ;Register C
tc0_sr          MM	0xFFFA0020	32      ;Status Register
tc0_ier         MM	0xFFFA0024	32      ;Interrupt Enable Register
tc0_idr         MM	0xFFFA0028	32      ;Interrupt Disable Register
tc0_imr         MM	0xFFFA002C	32      ;Interrupt Mask Register
;
tc1_ccr         MM	0xFFFA0040	32      ;TC1
tc1_cmr         MM	0xFFFA0044	32
tc1_cv          MM	0xFFFA0050	32
tc1_ra          MM	0xFFFA0054	32
tc1_rb          MM	0xFFFA0058	32
tc1_rc          MM	0xFFFA005C	32
tc1_sr          MM	0xFFFA0060	32
tc1_ier         MM	0xFFFA0064	32
tc1_idr         MM	0xFFFA0068	32
tc1_imr         MM	0xFFFA006C	32
;
tc2_ccr         MM	0xFFFA0080	32      ;TC2
tc2_cmr         MM	0xFFFA0084	32
tc2_cv          MM	0xFFFA0090	32
tc2_ra          MM	0xFFFA0094	32
tc2_rb          MM	0xFFFA0098	32
tc2_rc          MM	0xFFFA009C	32
tc2_sr          MM	0xFFFA00A0	32
tc2_ier         MM	0xFFFA00A4	32
tc2_idr         MM	0xFFFA00A8	32
tc2_imr         MM	0xFFFA00AC	32
;
tc0_bcr         MM	0xFFFA00C0	32      ;Block Control Register
tc0_bmr         MM	0xFFFA00C4	32      ;Block Mode Register
;
; Timer Counter 3,4,5 (TC)
;
tc3_ccr         MM	0xFFFA4000	32      ;Channel Control Register
tc3_cmr         MM	0xFFFA4004	32      ;Channel Mode Register
tc3_cv          MM	0xFFFA4010	32      ;Counter Value
tc3_ra          MM	0xFFFA4014	32      ;Register A
tc3_rb          MM	0xFFFA4018	32      ;Register B
tc3_rc          MM	0xFFFA401C	32      ;Register C
tc3_sr          MM	0xFFFA4020	32      ;Status Register
tc3_ier         MM	0xFFFA4024	32      ;Interrupt Enable Register
tc3_idr         MM	0xFFFA4028	32      ;Interrupt Disable Register
tc3_imr         MM	0xFFFA402C	32      ;Interrupt Mask Register
;
tc4_ccr         MM	0xFFFA4040	32      ;TC4
tc4_cmr         MM	0xFFFA4044	32
tc4_cv          MM	0xFFFA4050	32
tc4_ra          MM	0xFFFA4054	32
tc4_rb          MM	0xFFFA4058	32
tc4_rc          MM	0xFFFA405C	32
tc4_sr          MM	0xFFFA4060	32
tc4_ier         MM	0xFFFA4064	32
tc4_idr         MM	0xFFFA4068	32
tc4_imr         MM	0xFFFA406C	32
;
tc5_ccr         MM	0xFFFA4080	32      ;TC5
tc5_cmr         MM	0xFFFA4084	32
tc5_cv          MM	0xFFFA4090	32
tc5_ra          MM	0xFFFA4094	32
tc5_rb          MM	0xFFFA4098	32
tc5_rc          MM	0xFFFA409C	32
tc5_sr          MM	0xFFFA40A0	32
tc5_ier         MM	0xFFFA40A4	32
tc5_idr         MM	0xFFFA40A8	32
tc5_imr         MM	0xFFFA40AC	32
;
tc3_bcr         MM	0xFFFA40C0	32      ;Block Control Register
tc3_bmr         MM	0xFFFA40C4	32      ;Block Mode Register
;
; MultiMedia Card (MCI)
;
mci_cr          MM	0xFFFB4000	32      ;Control Register
mci_mr          MM	0xFFFB4004	32      ;Mode Register
mci_dtor        MM	0xFFFB4008	32      ;Data Timeout Register
mci_sdcr        MM	0xFFFB400C	32      ;SD Card Register
mci_argr        MM	0xFFFB4010	32      ;Argument Register
mci_cmdr        MM	0xFFFB4014	32      ;Command Register
mci_rspr        MM	0xFFFB4020	32      ;Response Register
mci_rdr         MM	0xFFFB4030	32      ;Receive Data Register
mci_tdr         MM	0xFFFB4034	32      ;Transmit Data Register
mci_sr          MM	0xFFFB4040	32      ;Status Register
mci_ier         MM	0xFFFB4044	32      ;Interrupt Enable Register
mci_idr         MM	0xFFFB4048	32      ;Interrupt Disable Register
mci_imr         MM	0xFFFB404C	32      ;Interrupt Mask Register
;
; USB Device Port (UDP)
;
usb_frm_num     MM	0xFFFB0000	32      ;Frame Number Register
usb_glb_stat    MM	0xFFFB0004	32      ;Global State Register
usb_faddr       MM	0xFFFB0008	32      ;Function Address Register
usb_ier         MM	0xFFFB0010	32      ;Interrupt Enable Register
usb_idr         MM	0xFFFB0014	32      ;Interrupt Disable Register
usb_imr         MM	0xFFFB0018	32      ;Interrupt Mask Register
usb_isr         MM	0xFFFB001C	32      ;Interrupt Status Register
usb_icr         MM	0xFFFB0020	32      ;Interrupt Clear Register
usb_rst_ep      MM	0xFFFB0028	32      ;Reset Endpoint Register
usb_csr0        MM	0xFFFB0030	32      ;Endpoint 0 Control and Status Register
usb_csr1        MM	0xFFFB0034	32      ;Endpoint 1 Control and Status Register
usb_csr2        MM	0xFFFB0038	32      ;Endpoint 2 Control and Status Register
usb_csr3        MM	0xFFFB003C	32      ;Endpoint 3 Control and Status Register
usb_csr4        MM	0xFFFB0040	32      ;Endpoint 4 Control and Status Register
usb_csr5        MM	0xFFFB0044	32      ;Endpoint 5 Control and Status Register
usb_csr6        MM	0xFFFB0048	32      ;Endpoint 6 Control and Status Register
usb_csr7        MM	0xFFFB004C	32      ;Endpoint 7 Control and Status Register
usb_fdr0        MM	0xFFFB0050	32      ;Endpoint 0 FIFO Data Register
usb_fdr1        MM	0xFFFB0054	32      ;Endpoint 1 FIFO Data Register
usb_fdr2        MM	0xFFFB0058	32      ;Endpoint 2 FIFO Data Register
usb_fdr3        MM	0xFFFB005C	32      ;Endpoint 3 FIFO Data Register
usb_fdr4        MM	0xFFFB0060	32      ;Endpoint 4 FIFO Data Register
usb_fdr5        MM	0xFFFB0064	32      ;Endpoint 5 FIFO Data Register
usb_fdr6        MM	0xFFFB0068	32      ;Endpoint 6 FIFO Data Register
usb_fdr7        MM	0xFFFB006C	32      ;Endpoint 7 FIFO Data Register
;
; Ethernet MAC (EMAC)
;
eth_ctl         MM	0xFFFBC000	32      ;EMAC Control Register
eth_cfg         MM	0xFFFBC004	32      ;EMAC Configuration Register
eth_sr          MM	0xFFFBC008	32      ;EMAC Status Register
eth_tar         MM	0xFFFBC00C	32      ;EMAC Transmit Address Register
eth_tcr         MM	0xFFFBC010	32      ;EMAC Transmit Control Register
eth_tsr         MM	0xFFFBC014	32      ;EMAC Transmit Status Register
eth_rbqp        MM	0xFFFBC018	32      ;EMAC Receive Buffer Queue Pointer
eth_rsr         MM	0xFFFBC020	32      ;EMAC Receive Status Register
eth_isr         MM	0xFFFBC024	32      ;EMAC Interrupt Status Register
eth_ier         MM	0xFFFBC028	32      ;EMAC Interrupt Enable Register
eth_idr         MM	0xFFFBC02C	32      ;EMAC Interrupt Disable Register
eth_imr         MM	0xFFFBC030	32      ;EMAC Interrupt Mask Register
eth_man         MM	0xFFFBC034	32      ;EMAC PHY Maintenance Register
eth_fra         MM	0xFFFBC040	32      ;Frames Transmitted OK Register
eth_scol        MM	0xFFFBC044	32      ;Single Collision Frame Register
eth_mcol        MM	0xFFFBC048	32      ;Multiple Collision Frame Register
eth_ok          MM	0xFFFBC04C	32      ;Frames Received OK Register
eth_seqe        MM	0xFFFBC050	32      ;Frame Check Sequence Error Register
eth_ale         MM	0xFFFBC054	32      ;Alignment Error Register
eth_dte         MM	0xFFFBC058	32      ;Deferred Transmission Frame Register
eth_lcol        MM	0xFFFBC05C	32      ;Late Collision Register
eth_ecol        MM	0xFFFBC060	32      ;Excessive Collision Register
eth_cse         MM	0xFFFBC064	32      ;Carrier Sense Error Register
eth_tue         MM	0xFFFBC068	32      ;Transmit Underrun Error Register
eth_cde         MM	0xFFFBC06C	32      ;Code Error Register
eth_elr         MM	0xFFFBC070	32      ;Excessive Length Error Register
eth_rjb         MM	0xFFFBC074	32      ;Receive Jabber Register
eth_usf         MM	0xFFFBC078	32      ;Undersize Frame Register
eth_sqee        MM	0xFFFBC07C	32      ;SQE Test Error Register
eth_drfc        MM	0xFFFBC080	32      ;Discarded RX Frame Register
eth_hsh         MM	0xFFFBC090	32      ;EMAC Hash Address High [63:32]
eth_hsl         MM	0xFFFBC094	32      ;EMAC Hash Address Low [31:0]
eth_sa1l        MM	0xFFFBC098	32      ;EMAC Specific Address 1 Low, First 4Bytes
eth_sa1h        MM	0xFFFBC09C	32      ;EMAC Specific Address 1 High, Last 2Bytes
eth_sa2l        MM	0xFFFBC0A0	32      ;EMAC Specific Address 2 Low, First 4Bytes
eth_sa2h        MM	0xFFFBC0A4	32      ;EMAC Specific Address 2 High, Last 2Bytes
eth_sa3l        MM	0xFFFBC0A8	32      ;EMAC Specific Address 3 Low, First 4Bytes
eth_sa3h        MM	0xFFFBC0AC	32      ;EMAC Specific Address 3 High, Last 2Bytes
eth_sa4l        MM	0xFFFBC0B0	32      ;EMAC Specific Address 4 Low, First 4Bytes
eth_sa4h        MM	0xFFFBC0B4	32      ;EMAC Specific Address 4 High, Last 2Bytes
;

